Journal of Circuits, Systems and Computers

COrdinate Rotation DIgital Computer (CORDIC) is commonly utilized for the computation of cosine/sine i.e., the trigonometric functions, singular value decomposition, in digital signal processing (especially in image/video processing), etc. This paper introduces an energy efficient quality tunable CORDIC architecture that computes the cosine/sine values of any required angle in real-time, and is thus well suited for real time DSP applications, especially for image or video processing applications. The proposed architecture reduces the latency and overcomes data dependency by simultaneously performing all the five iterations, that may vary depending upon the desired energy efficiency. The novelty of this architecture is that, desired quality can be achieved by selecting one out of the available three modes. In order to assess the efficacy of the suggested architecture, some benchmark images are processed using the Discrete Cosine Transform (DCT) coefficients obtained via the proposed design. Energy saving is achieved at the cost of slight acceptable degradation in the output image quality. Further, the simulation results show that the proposed architecture is 92.3%, 2.8% and 49.08% more energy efficient than the existing basic, scale-free and lookahead CORDIC architectures, respectively.

This paper presents the quasi-adiabatic logic for low power powered by two phase sinusoidal clock signal. The proposed logic called two phase adiabatic dynamic logic (2PADL) realizes the advantages of energy efficiency through the use of gate overdrive and reduced switching power. It has a single rail output and the proposed logic does not require the complementary input signals for any of its variables. The 2PADL logic is operated by two complementary clock signals acting as power supply. The validation of the proposed logic is carried out through practical circuits such as (i) sequential circuits using energy recovery technique suitable for memory circuits, (ii) an adiabatic carry look ahead adder (CLA) designed using 2PADL to study the speed performance and to prove its energy efficiency across a range of frequencies and (iii) a multiplier circuit using 2PADL compared against CMOS counterpart. The CLA adder is also implemented using the other static adiabatic logics, namely, quasi static energy recovery logic (QSERL), clocked CMOS adiabatic logic (CCAL) and conventional static CMOS logic to compare against 2PADL and validate its power advantages. The performance of the CCAL logic is tested for higher frequencies by implementing the widely presented CLA circuit. The result proves that the design is energy efficient and operates up to the frequency of 600 MHz. The simulation was carried out using industry standard Cadence® Virtuoso tool using 180nm technology library files.

A significant amount of processor power is required to handle packet processing in high speed data networks and taking it to the hardware helps processor to save its energy for other processes. In this study, an Offload Engine IP core that provides the hardware acceleration of UDP/IP protocol stack together with a few other network protocols is introduced. Furthermore, the IP core is equipped with PCI Express (PCIe) interface so as to communicate with applications running on a host PC. Consequently, a processor core deals with only the data processing, while the IP core takes care of the packet processing as per the protocol. The design and implementation of the IP core are verified and tested on an FPGA board; its area utilization and supported features are compared against several competitive designs from the literature. According to these results, the IP core is proved to be a useful one for those network applications that require a hardware-accelerated network protocol stack.

Fault-tolerant Manhattan routing algorithms aim at finding a Manhattan path between the source and destination nodes and route around all faulty nodes. However, besides faulty nodes, some nonfaulty nodes that are helpless to make up a fault-tolerant Manhattan path should also be routed around. How to label such nonfaulty nodes efficiently is a major challenge. We propose a path-counter method. It can label such nodes with low time-complexity by counting every node’s fault-tolerant Manhattan paths to the source or destination node. During the path-counting procedure, no available nodes will be sacrificed under arbitrary fault distribution. Compared with fault-block model based work, our proposed method is independent of fault distribution, so its computational complexity is very low.

Nowadays, multilevel inverters (MLI) are receiving remarkable attention due to salient features like less voltage stress on switches and low total harmonic distortion (THD) in output voltage. However, the required switch count increases with number of voltage levels. This paper presents a new topology for asymmetric multilevel inverter as a fundamental block. Each block generates 13-level output voltage using eight switches and four unequal dc voltage sources. The proposed configuration offers special features such as reduced number of switches, isolated dc sources, cost economy, less complex and modular structure than other similar contemporary topologies. Moreover, significant reduction in voltage stress on the circuit switches can be achieved. Comparative studies of proposed topology with the conventional and recent topologies have been presented in terms of power switches, gate driver circuit requirement, isolated dc voltage sources and total standing voltage. Multicarrier-based sinusoidal pulse width modulation (SPWM) scheme is adopted for generating switching signals using dSPACE real-time controller. In addition, proposed topology offers a fewer number of ON-state switches that lead to reduction in power loss. The proposed topology is validated through simulation and experimental implementation.

The technology scaling impact on FinFET-based Field-Programmable Gate Array (FPGA) components (Flip-Flops and Multiplexers) and cluster metrics is evaluated for technology nodes starting from 20nm down to 7nm. Power consumption, delay and energy (Power Delay Product, or PDP) trends are reported with FinFET technology scaling. Cluster metrics are then evaluated based on three benchmarking circuits: 2-bit adder, 4-bit NAND and cascaded flip-flops chain. The study shows that power, delay and PDP of the FPGA cluster are improved as we scale down the technology. An example for improvement is that for 7nm 2-bit adder, circuit speed is 15% higher than its value at 20nm and PDP at 7nm is reduced by 43% compared to its value at 20nm. The impacts of temperature and threshold voltage variations on FPGA cluster performance are also reported after evaluating a 2-bit adder circuit as a benchmark which is then used to calculate the design constraints to meet 99.9% yield percentage.

This work deals with the passive control-based chaos synchronization with circuit design for secure communication. First, the numerical simulation and electronic circuit design of a simple five-term chaotic system are performed. The numerical simulation and electronic circuit design outputs have confirmed each other. Then, the passive control method is applied for synchronizing two identical five-term chaotic systems using only one state control signal. After the synchronization study, design and analysis for secure communication by chaotic masking method are conducted in Matlab–Simulink platform. Finally, an electronic circuit design is performed for the designed communication system. In the designed communication system with Matlab–Simulink platform and electronic circuit design, information signal which is sent from the transmitter unit is successfully retrieved at the receiver unit. As a result, the electronic circuit design has shown that a single state passivity-based synchronization signal can be effectively used for secure data communication applications for the real environment.

For S-band applications, a microstrip fractal antenna is designed by extending narrow impedance bandwidth into wide impedance bandwidth with use of partial ground plane. In the designed fractal antenna, the six elliptical slots in ground plane and two elliptical slots in radiating patch are embedded to improve the depth of return loss. Further, the parametric study is performed on width of microstrip feeding line, position/size of ellipses in radiating patch and ground plane to achieve mismatch loss $\le$ 0.044dB and power delivered to antenna 99%, i.e., return loss $(S_{11})\le -20$dB for S-band. The simulated antenna results are obtained using electromagnetic solver software and fabricated antenna results are measured using Vector Network Analyzer Bench MS46322A and they are found to be in good agreement.

In this paper, a modified methodology to find an optimal T-S fuzzy model based on an extended heterogeneous Multi-swarm PSO (MsPSO) algorithm is developed in order to enhance search ability of the classical MsPSO algorithm. However, this simple MsPSO algorithm search behavior is not always optimal to find the potential solution to a special problem, and it may trap the individuals into local regions leading to premature convergence. To overcome this drawback, two parameter automation strategies (inertia weight and acceleration coefficients) are introduced based on gray relational analysis in MsPSO to guarantee a highly accurate model. The performance of the proposed algorithm is evaluated by adopting standard tests and indicators which are reported in the specialized literature. The numerical results demonstrate that the proposed algorithm is significantly better than the original MsPSO algorithm and the rest of compared algorithms according to mean and standard deviation (std) tests. Next, to further validate the generalization ability of the Improved OptiFel approach, the proposed algorithm is secondly applied on the BoxJenkins Gas Furnace system. Then, the improved OptiFel method is applied to an irrigation station process in order to provide an optimal T-S fuzzy model. Compared to the other existing methods, we achieve the result that the improved OptiFel can generate good fuzzy model with high accuracy and strong generalization ability.

In the process of image acquisition and transmission, data can be corrupted by impulse noise. This paper presented the removal of impulse noise in medical image by using Very Large Scale Integrated circuit (VLSI) implementation. The Low Cost Reduced Simple Edge Preserved De-noising (LCRSEPD) technique is introduced using Low Area Carry Select Adder (CSLA) to remove the salt and pepper noise instead of normal adder. Thus, LCRSEPD technique preserves visual performance and edge features in terms of quality and quantitative evaluation. By optimizing the architecture, low cost RSEPD can achieve low computational complexity that will reflect in area, power and delay. Compared to the previous VLSI implementations, the LCRSEPD implementation with CSLA adder has achieved good medical image quality and less hardware cost due to the reduction of area, power and delay.

Template warping is a widely used approach in the pose recovery field. Due to its flexibility, template warping is especially useful in monocular video motion tracking. Tracking accuracy is largely determined by the appearance of the 3D model. Moreover, the appearance of the 3D model plays a very important role in template warping. However, accurate tracking results are difficult to obtain because hand estimated 3D models are prone to inaccuracies (the appearance of 3D models is commonly initialized by the user based on the first frame of video footage; the result is a hand estimated 3D model). In order to overcome this problem, we propose an iterative optimization process that estimates the appearance of the 3D model during tracking. Our results show that our proposed 3D model estimation achieves better performance than the hand model initialization estimation.

In this paper, we extend an information-theoretic approach of computer performance evaluation to supercomputers. This approach is based on the notion of computer Capacity which can be estimated relying solely on the description of computer architecture. We describe the method of calculating Computer Capacity for supercomputers including the influence of the architecture of communication network. The suggested approach is applied to estimate the performance of three of the top 10 supercomputers (according to TOP500 June-2016 list) which are based on Haswell processors. For greater objectivity of results, we compared them relatively to values of another supercomputer which is based an Ivy Bridge processors (this microarchitecture differs from Haswell). The obtained results are compared with values of TOP500 LINPACK benchmark and theoretical peak and we arrive at conclusions about the applicability of the presented theoretical approach (nonexperimental) for performance evaluation of real supercomputers. In particular, it means that the estimations of the computer capacity can be used at the design stage of the development of supercomputers.

The fully depleted Silicon-On-Insulator MOSFETs (FD-SOI) have shown high immunity to short channel effects compared to conventional bulk MOSFETs. The inclusion of gate underlap in SOI structure further improves the device performance in nanoscale regime by reducing drain induced barrier lowering and leakage current ($I_{\mathrm{\text{OFF}}}$). However, the gate underlap also results in reduced ON current ($I_{\mathrm{\text{ON}}}$) due to increased effective channel length. The use of high-$k$ material as a spacer region helps to achieve the higher $I_{\mathrm{\text{ON}}}$ but at the cost of increased effective gate capacitance ($C_{\mathrm{\text{GG}}}$) which degrades the device performance. Thus, the impact of high-$k$ spacer on the performance of underlap SOI MOSFET (underlap-SOI) is studied in this paper. To fulfil this objective, we have analyzed the performance parameters such as $C_{\mathrm{\text{GG}}}$, $I_{\mathrm{\text{ON}}}$, $I_{\mathrm{\text{OFF}}}$, $I_{\mathrm{\text{ON}}}$/$I_{\mathrm{\text{OFF}}}$ ratio and intrinsic transistor delay (CV/I) with respect to the variation of device parameters. Various dielectric materials are compared to optimize the $I_{\mathrm{\text{ON}}}$/$I_{\mathrm{\text{OFF}}}$ ratio and CV/I for nanoscale underlap-SOI device. Results suggest that the HfO₂ of 10nm length is optimum value to enhance device performance. Further, the higher underlap length is needed to offset the exponential increase in $I_{\mathrm{\text{OFF}}}$ especially below 20nm gate length.

This paper proposes a continuous-rate clock-data-recovery (CDR) circuit that covers a data rate range of 500Mbps to 1.7Gbps. The proposed CDR is based on the phase interpolation principle and implemented in 130nm CMOS. The design utilizes digital voter and phase control logic instead of analog charge pump and filter, which facilitates migration among different technologies. To avoid the phase interpolator (PI) getting into the nonlinear region, multiple modes are selected to limit the frequency range of the sampling clock within 500MHz to 1GHz. A 5mm² test chip is fabricated, where the CDR core occupies 0.359mm² of silicon area. The PI achieves a resolution of 7 bits and a good linearity of 0.9955. The proposed CDR also achieves a BER less than 10${}^{-12}$ and has a frequency tracking range of $\pm 1466$ppm. The power consumed by the proposed CDR is 32.6mW/Gbps.

In this paper, a novel adaptive tuning method of PID neural network (PIDNN) controller for nonlinear process is proposed. The presented method utilizes an improved gradient descent method to adjust PIDNN parameters where the margin stability will be employed to get high tracking performance and robustness with regard to external load disturbance and parameter variation. Simulation results show the effectiveness of the proposed algorithm compared with other well-known learning methods.

Chaotic systems with a curve of equilibria have attracted considerable interest in theoretical researches and engineering applications because they are categorized as systems with hidden attractors. In this paper, we introduce a new three-dimensional autonomous system with cubic equilibrium. Fundamental dynamical properties and complex dynamics of the system have been investigated. Of particular interest is the coexistence of chaotic attractors in the proposed system. Furthermore, we have designed and implemented an electronic circuit to verify the feasibility of such a system with cubic equilibrium.

With the increasing requirements of transmitting larger amounts of diverse video and image data, the PCI express (PCIe) interface has been extensively used in high-speed digital systems for multimedia processing and communication. However, the existing PCIe transmission methods are not efficient to transmit multi-channel videos on FPGA processors, as they waste PCIe bandwidth and hardware resources. In this paper, an efficient PCIe transmission method for multi-channel video is presented on an FPGA processor. First, to reduce the programmed I/O (PIO) write latency, the command caching method is adopted. The traditional DMA descriptors are transformed into DMA commands, which are smaller, and the command buffer is used to store these commands. Second, a dynamic splicing mechanism is proposed for data transmission and commands the scheduling separately. The multi-type data is transmitted concurrently in this dynamic splicing mechanism. Moreover, the adjacent commands are spliced into one command, which reduces the DMA initiation times. Finally, the direct kernel memory access technique and timer self-feedback monitor technique are applied to improve the transmission efficiency and enhance the system reliability. The experimental results show that the transmission efficiency of the proposed method is increased by nearly 30% compared with other conventional methods, and the highest measured transfer rate is 1631 Mbytes/s on write and 1582 Mbytes/s on read, which reaches 84.4% of the theoretical maximum.