Journal of Circuits, Systems and Computers

The current energy scenario in the world considering the overconsumption of fossil fuels as well as its disastrous impact on environment calls for the promotion of renewable resources to take part in the growth towards sustainable development. With the penetration of such intermittent renewable energy sources into the existing grid, it not only enhanced the capability of the grid but also posed challenges regarding system stability. A practical solution to these problems by means of a new technological concept called “electric springs” is presented in this paper which enhances the system stability and provides voltage regulation for the same. Reviewing the various analyses, control methodologies as well as applications regarding the electric spring provides the confidence to further analyze its scope in large-scale power distribution system.

Objective: This research aims to survey the efforts of researchers in response to the new and disruptive technology of skin cancer apps, map the research landscape from the literature onto coherent taxonomy, and determine the basic characteristics of this emerging field. In addition, this research looks at the motivation behind using Smartphone apps in the diagnosis of skin cancer and in health care and the open challenges that impede the utility of this technology. This study offers valuable recommendations to improve the acceptance and use of medical apps in the literature. Methods: We conducted a comprehensive survey using the keywords “skin cancer,” “apps,” and “Smartphone” or “m-Health” in different variations to find all the relevant articles in three major databases: Web of Science, Science Direct, and IEEE Xplore. These databases broadly cover medical and technical literature. Results: We found 110 articles after a comprehensive survey of the literature. Out of the 110 articles, 46 present actual attempts to develop and design medical apps or share certain experiences of doing so. Twenty-eight articles consist of analytical studies on the incidence of skin cancer, the classification of malignant cancer or benign cancer, and the methods of prevention and diagnosis. Twenty-two articles comprise studies that range from the evaluative or comparative study of apps to the exploration of the desired features for skin cancer detection. Fourteen articles consist of reviews and surveys that refer to actual apps or the literature to describe medical apps for a specific specialty, disease, or skin cancer and provide a general overview of the technology. New research direction: With the exception of the 110 papers reviewed earlier in results section, the new directions of this research were described. In state-of-the-art, no particular study presenting watermarking and stenography approaches for any type of skin cancer images based on Smartphone apps is available. Discussion: Researchers have attempted to develop and improve skin cancer apps in several ways since 2011. However, several areas or aspects require further attention. All the articles, regardless of their research focus, attempt to address the challenges that impede the full utility of skin cancer apps and offer recommendations to mitigate their drawbacks. Conclusions: Research on skin cancer apps is active and efficient. This study contributes to this area of research by providing a detailed review of the available options and problems to allow other researchers and participants to further develop skin cancer apps, and the new directions of this research were described.

This work presents a low-power biopotential amplifier integrated circuit (IC) for implantable neural recording prosthetic devices which have been implemented using 0.18-$\mu$m CMOS technology. The proposed neural recording amplifier is based on a capacitive-feedback architecture and utilizes a low-power two-stage source-degenerated operational transconductance amplifier (OTA) with a modified current buffer compensation for large open-loop gain, low-noise and wide bandwidth. The designed amplifier achieves a measured gain of 39.2dB with a bandwidth between 0.25Hz to 28kHz, integrated input referred noise of 5.79$\mu$Vrms and noise efficiency factor of 3.16. The IC consumes 2.4$\mu$W at 1.2V supply and the die area is 0.09mm².

In this paper, basic step-up switched dc/dc converters and its quasi structures are proposed. In dc/dc converters, the operation of the converters can be changed by changing the values of the elements and other parameters such as duty cycle, so the complete analysis of the basic step-up switched dc/dc converter (SSC) in different operating modes is presented. It is shown that, SSC has three different operating modes, which include synchronous operation of diodes (SOD), asynchronous operation of diodes (AOD), and boundary mode (BM). These operating modes are related to the diodes ON and OFF time. Critical inductors are calculated in BM and their values are investigated under various conditions. Inductors current ripple and the output voltage ripple are also calculated. The precise power losses analysis and small signal (SS) analysis for SSC are presented. The high voltage gain quasi structures are introduced and all of the proposed structures are compared with conventional structures. Finally, in order to verify the accuracy of the claims, the experimental results are presented.

Many crucial dependable and secure services including atomic commitment, consensus and group membership, and middleware services (such as replica, communication and transaction services) use fault detectors. Through the use of fault detectors, the overlying service can be exempted from failure treatment and synchronization requirements. Fault detection is essential for proving that the services carried out are correct.

In this paper, we first identify the necessary conditions to detect faults in a message passing system where multiple disjoint paths exist between each pair of endpoints. We then present the first fault detection protocol capable of detecting message meta-data modification in the presence of various message interferences in addition to other faults including omission faults, message replay and spurious messages using disjoint paths, where paths with faults are not known a priori. In addition, it authenticates message origins allowing Sybil attacks to be detected, identifies faulty paths, and classifies faults in the presence of multiple messages sent by various system processes. We establish the completeness and soundness properties of the proposed algorithm, i.e., it detects each considered fault and each detected fault is an actual fault, respectively. We also show that our algorithm does not yield a significant packet size and delay overheads. The algorithm shows the viability of the use of disjoint paths in fault detection.

Two new analog squarer circuits employing only seven MOS transistors are proposed in this study. The second proposed analog squarer is derived from the first one with slight modifications. MOS transistors used in both of the proposed analog squarers are operated in the saturation region. They are constructed as voltage input and current output. They have high input and high output impedances; consequently, they can be connected with other structures easily. Both of the proposed analog squarers have low power dissipation. However, they need some active component matching conditions. A four quadrant analog multiplier is given as an application example. Workability of the proposed analog squarers is verified by some SPICE simulation results. Additionally, some experimental tests are achieved.

A 400$\mu$W near-threshold supply class-C voltage controlled oscillator (VCO) with amplitude feedback loop and auto amplitude control (AAC) is proposed in this paper. The amplitude feedback loop and AAC ensure the robust startup of the proposed VCO and automatically adapts it to the class-C mode in steady state. Consequently, ultra-low power can be achieved in AAC mode and low phase noise, high swing can be achieved in AAC off mode. The proposed VCO with AAC gets ultra-low power consumption by limiting the oscillating amplitude and driving the proposed VCO into the deep Class-C mode. Additionally, the peak value detector is employed in this work to boost the controlling voltage of capacitors bank. Thus, a low on resistance of switch transistors is obtained, which increases the Q value of capacitors bank. The simulated phase noise is $-$124.5dBc/Hz at 1MHz offset with the 1.16GHz oscillation frequency. In this case, the figure-of-merit including tuning range (FOM_T) of proposed VCO is $-$195dBc/Hz. The proposed VCO is fabricated in SMIC 40nm CMOS process and consumes 0.62mA from 0.65V supply. The measured phase noise is $-$109dBc/Hz and FOM_T is $-$179dBc/Hz.

Modeling for an unknown plant is a very important and primary task in the control system engineering. By using this established model, an adequate controller can be further designed to meet certain control specifications. This paper will propose a new modeling method which is based on the infinite impulse response (IIR) digital filter structure. A modified particle swarm optimization (PSO) with multiple subpopulations is utilized to solve for the IIR filter coefficients to model an unknown digital system. The developed PSO algorithm is able to overcome the multimodal error surface problem that often occurs in the system modeling of IIR digital filter. Finally, three different kinds of digital systems are examined to demonstrate the feasibility of the proposed method, including the same system order and reduced order structures. It is concluded from several simulation results that the proposed method has an excellent performance on solving the IIR digital modeling problem.

Passive synthesis of fractional driving-point immittance function is one of the most important research topics in fractional circuits. The synthesis method for a class of fractional driving-point immittance function is proposed in this paper. Firstly, the immittance function of passive fractional circuit is transformed to multivariable positive-real function by proper variable substitution. Secondly, to synthesize the function, except one variable, other high-order variables are transformed to the combination of products of different one-order variables by introducing new variables. Thirdly, synthesize the new function by traditional method. At last, substitute elements inversely twice and the final circuit for fractional driving-point immittance function can be achieved. The method is verified by giving synthesis demonstration.

The efficiency of residue number system depends on the reverse converter due to several modulo operations like addition, subtraction and multiplication. In this paper, a design of new four moduli set $\{2^{n-1},2^n-1,2^n+1,2^{2n+1}-1\}$, reverse converter is presented. The moduli set have moduli with length ranging from ($n-1$) to ($2n+1$)-bits. The reverse conversion for moduli set $\{2^{n-1},2^n-1,2^n+1\}$ has been optimized in existing state of art. Thus, proposed converter is based on two new moduli set $\{2^{n-1}(2^{2n}-1),2^{2n+1}-1\}$ and utilizes the mixed radix conversion. This converter is memoryless, and occupies least area. The proposed converter is based on carry save adder (CSA) and modulo adder enabling more speed and less hardware complexity for dynamic range of $5n$-bit, offering good area-delay product.

Coordinate rotation digital computer (CORDIC) algorithm has been widely used in modern digital communication systems such as all-digital phase-locked loop, fast Fourier transform and direct digital frequency synthesizers. Precision of the CORDIC algorithm implemented using pipelined architecture has to be guaranteed by increasing the number of iterations, which leads to large delay, excessive consumption of hardware resource and other problems, unfavorable for applications calling for high real-time performance and low power consumption. In this paper, through integrated use of binary to bipolar recoding, angle domain folding, merging iteration and optimized lookup table, an iteration-free CORDIC algorithm was proposed, with which it takes only two clock cycles to get the output, and it enables certain improvements in hardware consumption and output precision when compared with other basic implementation methods.

In this brief, we present the design and evaluation of a high speed and energy-efficient truncated multiplier for unsigned multiplication, such that the average absolute error due to truncation and rounding is kept minimal. The proposed algorithm eliminates a few least significant Partial Product (PP) bits and adds correction bias at appropriate PP bit positions to minimize the total error. From the literatures reviewed, it is clear that there is scope for reducing delay in multiplication using sutras of ancient vedic mathematics. This work uses a simple “crosswise and vertical sutra” of Vedic mathematics to generate PP bits. The proposed methodology groups the input into $n$/2 bits, eliminates least subgroup multiplication ($A_{n∕2-\mathrm{\text{LSB}}}\times B_{n∕2-\mathrm{\text{LSB}}}$) and deletes few least significant bits in other subgroup multiplications to reduce area and power dissipation. In addition, correction biase are added at appropriate bit positions to reduce the overall absolute error due to the elimination of few PP bits and rounding of final product. Experimental evaluation of the proposed truncated design is carried out through structural level VHDL modeling and simulations using Synopsys design compiler. Performance analysis revealed Chip-Area Ratio (CAR%) to be 33.81% and Power-Delay Product (PDP) of 14.84pJ of proposed truncated design for an $8\times 8$ multiplication.

In several pseudorandom built-in self-test (BIST) circuits, the applied test vectors will be generated by a linear feedback shift register (LFSR). This type of test pattern generator (TPG) may generate some repeated test patterns, which unnecessarily increases the test power without contributing much to the fault coverage. Based on the vast designs of TPG engine, the chip area also increases by contributing for the overall power consumption of the IC. This paper presents an approach called low power — bit complements test vector generation (LP-BCTVG) technique with bipartite (half fixed) and bit insertion (either 0 or 1) techniques. In order to reduce the test power, the LP-BCTVG inserts appropriate intermediate vectors in between consecutive test vectors generated by LFSR circuit. Hence, the application of final output vectors of LP-BCTVG circuit over circuit under test decreases the test power compared with LFSR-based BIST. By complementing the output bits of LP-BCTVG, we can reduce the bulkiness of TPG engine approximately by half. This further contributes to the reduced IC size. The obtained simulation results prove that this technique can reduce the overall test power consumption along with better fault coverage when compared with LFSR-based BIST and other recent methods. Here, the proposed approach has been tested on several ISCAS’85, ISCAS’89 and ITC’99 benchmark circuits.

In this paper, a power-enhanced active rectifier with high precision of current detection for piezoelectric energy harvesting (PEH) system is presented. A traditional two-stage active rectifier is adopted, which includes a first-stage negative voltage converter and an active diode. A comparator with offset control technique is proposed; thus the input-referred offset voltage of the proposed comparator can be less than 1mV. The current detected accuracy of the proposed offset-controlled comparator (OCC) is improved by more than 10 times over a traditional comparator. Output oscillations of the OCC are dramatically reduced attributing to the high precision of current detection. In addition, the OCC is also able to prevent the reverse leakage current. The design is implemented in an SMIC 0.18$\mu$m standard CMOS technology with a chip area of 0.22mm². The measurement results show that the maximum output power, power conversion efficiency and figure of merit are 23.3$\mu$W, 90%, and 0.9, respectively, when the open-circuit voltage is 2.4V. The proposed rectifier can be self-powered without the additional external supply.

Scratch-Pad Memories (SPMs) have been increasingly used in real-time and embedded systems. However, it is still unknown and challenging to reduce the worst-case execution time (WCET) for hybrid SPM-cache architecture, where an SPM and a cache memory are placed on-chip in parallel to cooperatively improve performance and/or energy efficiency. In this paper, we study four SPM allocation strategies to reduce the WCET for hybrid SPM-caches with different complexities. These algorithms differ by whether or not they can cooperate with the cache or be aware of the WCET. Our evaluation shows that the cache-aware and WCET-oriented SPM allocation can minimize the WCET for real-time benchmarks with little or even positive impact on the average-case execution time (ACET).

Recently developed spin-based, racetrack memory (RM) shows great promise in enabling nonvolatile memory with unprecedented density and energy efficiency. RM-based technology will leverage the power and cost limit of main memory. However, main memory has random accessing patterns and makes racetrack shifting overhead variable that induces an unstable latency. This paper analyzes the shifting features in view of computing architecture by exploring the design space of RM. We propose RM-based pre-shifting and direction optimized policies to reduce the shifting overhead and to achieve a DRAM comparable performance without additional energy and area overhead. Experiments with a wide range of SPEC2006 benchmarks show the proposed methodology outperforms RM-based main memory without pre-shifting by 12% in energy consumption. Compared to DRAM-based main memory of the same capacity, the proposed methodology improves the energy consumption by 53% on average.

The increasing complexity of automotive electronics and the communication of cars with the external environment have led to extensive security issues. The car industry is moving towards the use of Ethernet backbones to improve the performance and reduce the complexity of in-car networks. In this paper, we propose a security solution for automotive Ethernet-based communications. We designed a hardware Media Access Control (MAC) layer based on the MAC Security Standard (MACsec) that considers the specific constraints of the automotive world in terms of latency, throughput and area. From a security point of view, our solution guarantees the confidentiality, integrity and authenticity of data. Furthermore, the system can be configured before synthesis to meet the security needs of the context in which the Ethernet communication is used. We synthesized our architecture on a low-power 28nm standard-cell CMOS technology, which is appropriate for automotive microcontrollers. The results show that our implementation is suitable for 100Mbps, 1Gbps and 10Gbps Ethernet speeds introducing less than 350ns of latency. The size of the circuit varies from 285 to 622 kgates depending on the required level of security and the required features.