Journal of Circuits, Systems and Computers

Scientific workflow is a common model to organize large scientific computations. It borrows the concept of workflow in business activities to manage the complicated processes in scientific computing automatically or semi-automatically. The workflow scheduling, which maps tasks in workflows to parallel computing resources, has been extensively studied over years. In recent years, with the rise of cloud computing as a new large-scale distributed computing model, it is of great significance to study workflow scheduling problem in the cloud. Compared with traditional distributed computing platforms, cloud platforms have unique characteristics such as the self-service resource management model and the pay-as-you-go billing model. Therefore, the workflow scheduling in cloud needs to be reconsidered. When scheduling workflows in clouds, the monetary cost and the makespan of the workflow executions are concerned with both the cloud service providers (CSPs) and the customers. In this paper, we study a series of cost-and-time-aware workflow scheduling algorithms in cloud environments, which aims to provide researchers with a choice of appropriate cloud workflow scheduling approaches in various scenarios. We conducted a broad review of different cloud workflow scheduling algorithms and categorized them based on their optimization objectives and constraints. Also, we discuss the possible future research direction of the clouds workflow scheduling.

Multilevel inverter (MLI) has become more popular in high power, high voltage industries owing to its high quality output voltage waveform. This paper proposes a novel single phase extendable type MLI topology. The term ‘extendable’ is included since the presented topology can be extended with maximum number of dc voltage sources to synthesize larger output levels. This topology can be operated in both symmetrical and asymmetrical conditions. The major advantages of the proposed inverter topology include minimum switching components, reduced gate driver circuits, less harmonic distortion and reduced switching losses. The comparative analysis based on the number of switches, dc voltage sources and conduction switches between the proposed topology and other existing topologies is presented in this paper. The comparison results show that the proposed inverter topology requires fewer components. The performance of the proposed MLI topology has been analyzed in both symmetrical and asymmetrical conditions. The simulation model is developed using MATLAB/SIMULINK software to verify the performance of the proposed inverter topology and also the feasibility of the presented topology during the symmetrical condition has been validated experimentally.

In time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches, caused by the limited bandwidth of input signal traces and sample circuits, seriously deteriorate the spurious-free dynamic range (SFDR) of the system. This paper analyzes the influence of bandwidth mismatch errors under different sampling sequences. Eventually, based on a randomization technique and the simulated annealing algorithm (SAA), a bandwidth mismatch optimization technique is presented that can work well with other bandwidth mismatch calibration methods. The behavior simulation results indicate that an improvement of 7dB in the SFDR can be achieved with this technique in a 16-channel TI-ADC after timing and gain calibration.

In this research paper, a voltage mode second order universal filter using Four Terminal Floating Nullor (FTFN) is presented. The proposed design uses Three Input Single Output (TISO) for the realization of all filter responses namely Low Pass Filter (LPF), High Pass Filter (HPF), Band Pass Filter (BPF), Notch Filter (NF) and All Pass Filter (APF) by using proper input selection. The analog building block, FTFN is simply realized with two commercially available AD844 ICs. The proposed second order universal filter comes with a single FTFN block with four passive components in which no component matching is required for filter realization. The universal filter is well verified using PSPICE simulation. In addition, experimental verification for the second order APF has been performed that confirms the theoretical expectations.

This paper proposes a full-band calibration scheme of timing mismatch for Time-Interleaved Analog-to-Digital Converters (TI-ADC) based on Automatic Identification (AI) detection scheme. Besides estimating the value of timing mismatch, AI detection scheme also judges the odd–even property of the Nyquist zone (NZ) which the input signal belongs to and thus adaptively adjusts the calibration polarity for full-band application. On the other hand, Successive-Approximation-Register (SAR) correction technique is employed to speed up the convergence process of calibration with low cost. The efficiency of the proposed calibration scheme is verified by MATLAB simulation and implementation on PCB. Both results show that with an input signal whose bandwidth is within any NZ, the proposed calibration methodology is effective. Compared with the traditional calibration schemes, the proposed calibration method achieves fast convergence speed with $6\times 10^3$ samples and costs less hardware with 2.1k gate counts.

Simulation of inductors has been a very popular area of analog circuit research and the alternative choice for realizing inductor-based circuits in integrated circuits. In this paper, lossless, grounded and floating inductor topologies using current-controlled-current-feedback amplifier (CC-CFA) with single grounded capacitor are presented. The proposed topologies can be tuned electronically by changing the biasing current of the CC-CFA. Two topologies for grounded inductor simulator employ two CC-CFA and one grounded capacitor. One topology for floating inductor simulator employs three CC-CFA and one grounded capacitor. The performance of the grounded and floating inductor simulators are demonstrated on resonant circuits. The theoretical analysis is verified by PSPICE simulation results.

Wireless sensor networks (WSNs) provide acceptable low cost and efficient deployable solutions to execute the target tracking, checking and identification of substantial measures. The primary step necessary for WSN is to organize all the sensor nodes in their positions to build up an effective network. In the sensor deployment model, Target COVerage (TCOV) and Network CONnectivity (NCON) are the basic issues in WSNs that have obtained significant consideration in sensor deployment. This paper intends to develop an intelligent context awareness algorithm for sensor deployment process in WSN. Accordingly, the process is divided into two phases. In the first phase, the TCOV process is performed, whereas the second phase of the algorithm establishes NCON among the sensors. An objective model to meet both TCOV and NCON is formulated as a minimization problem. The problem is solved using FireFly (FF) optimization to determine the optimal locations for sensors. It leads to an intelligent sensor deployment model that can determine the optimal locations for the sensors in the WSN. Further, the proposed FF-TCOV and FF-NCON models are compared against the conventional algorithms, namely, genetic algorithm, particle swarm optimization, artificial bee colony, differential evolution and evolutionary algorithm-based TCOV and NCON models. The results achieved from the simulation show the improved performance of the proposed technique.

This paper investigates a time-to-digital converter (TDC) that employs interpolation and time stretching techniques for digitizing the time interval between the rising edges of two input signals as well as increasing the resolution. In the proposed TDC, interpolation is performed based on a dual-slope conversion. The proposed converter eliminates the comparator offset voltage error and the comparator parasitic capacitor error compared with the TDCs that have been proposed previously. The features of the converter consist of the high accuracy and high resolution due to elimination of errors and usage of the analog interpolation structure. Moreover, it does not use gated delay lines in its structure and has the advantage of low sensitivity to the temperature, power supply and process (PVT) variations. For validation, the proposed TDC is designed in TSMC 0.18$\mu$m CMOS technology and simulated by Hspice simulator. The comparison between the theoretical and simulation results confirms the benefits of the proposed TDC operation. The results prove that it can be employed for high speed and resolution applications.

A subthreshold MOS-based pseudo-resistor featuring a very high value and ultra-low distortion is proposed. A bandpass neural amplifier with a very low high-pass cutoff frequency is designed, to demonstrate the linearity of the proposed resistor. A BJT less CTAT current generator has been introduced to minimize the temperature drift of the resistor and make tuning easier. The standalone resistor has achieved 0.5% better linearity and a 12% improved temperature coefficient over the existing architectures. A neural amplifier has been designed with the proposed resistor as a feedback element. It demonstrated 31dB mid-band gain and a low-pass cutoff frequency of 0.85Hz. The circuit operates from a 1V supply and draws 950nA current at room temperature.

In this paper, gray ROM-based encoder is proposed for the implementation of flash ADCs encoder block based on converting the conventional 1-of-$N$ thermometer codes to 2-of-$M$ codes ($M=\frac{3}{4}N$). The proposed gray ROM-based encoder is composed of three stages. In the first stage, the thermometer codes are converted to 2-of-$M$ codes by the use of two-input AND and four-input merged AND–OR gates. In the second stage, 2-of-$M$ codes are turned to $n-1$ gray codes and a binary code by a quasi-gray ROM encoder and a binary ROM encoder, respectively. Finally, in the third stage, $n-1$ MSB bits and LSB bit are determined by a quasi-gray-to-binary converter and a CMOS inverter, respectively. The advantages of the proposed encoder over the conventional encoder are higher speed of second stage, low power, low area and low latency with the same bubble and meta-stability errors removing capability. To demonstrate the mentioned specifications, two 5-bit flash ADCs with the conventional and proposed encoders in their encoder blocks are analyzed and simulated at 2-GS/s and 3.2-GS/s sampling rates in 0.18-$\mu$m CMOS process. Simulation results show that the ENOBs of flash ADCs with the conventional and proposed encoders are equal. In this case, the proposed encoder outputs are determined to be approximately 30ps faster than the conventional encoder at 2 GS/s. The power dissipations of the conventional and proposed encoders were 19.50mW and 13.90mW at 3.2-GS/s sampling rate from a 1.8-V supply and also the latencies of the encoders were 4 ADC clocks and 3 ADC clocks, respectively. In this case, the number of D-FFs and logic gates of the proposed encoder is decreased approximately by 37% when compared to the conventional encoder.

This paper presents the synthesis and analysis of reconfigurable frequency filter with differential input and differential output terminals and its experimental verification. The inner structure of the filter has single-ended form, i.e., filter behaves as the so-called pseudo-differential circuit. Filtering function can be electronically reconfigured between low-pass (LP) and band-pass (BP) responses. Active elements of the filter are differential voltage buffer (DVB) as an input stage and modified current differencing unit (MCDU) together with modified current summing unit (MCSU) as the inner and also output stage. Each of the important parameters of the filter (angular pole frequency, quality factor and pass-band gain) is electronically controllable by parameters of these active elements used. Some of the parameters of the filter are controlled by two independent parameters, i.e., are dual-controlled, which enables the extended electronic controllability. The proposed topology operates in the voltage mode and both input nodes have high input impedance. Expected behavior of the filter is analyzed and verified by PSpice simulations using CMOS models of above-mentioned active elements. Moreover, features of the filter in both configurations were successfully verified also by experimental measurements using behavioral models of active elements.

In this study, we propose a modified partial differential equation (PDE)-based algorithm for image de-hazing. The algorithm possesses relatively low computational complexity and the core function of the PDE is easily amenable to hardware implementation. New contributions include the optimization and automated processing for dark and hazy images, avoiding manual parameter tuning. Additionally, the regularization parameter is computed adaptively from the binary mask of the input image. This is combined with a gradient-based metric for optimization to automatically determine stopping time of the algorithm for both types of images. The proposed scheme is fast and utilizes spatial or frequency domain filters to achieve illumination and reflectance component estimation without resorting to logarithms. Moreover, there is absence of halos in de-hazed images compared to previous work. Extensive experiments indicate that the proposed approach yields results comparable to or better than several works from the literature.

Comparator hysteresis is a memory phenomenon allowing outputs maintaining their past stable states until the input difference overcomes a given threshold voltage. In some applications, such as ADCs and memories, hysteresis is a deterministic error that should be minimized. In others, it can be considered as one of the design parameters, such as in implementing hysteresis control-based systems such as peak detectors and spectrum analyzers. In any case, the designer should be aware of how to estimate hysteresis to achieve the desired performances. This paper presents a mathematical approach to estimate hysteresis in clocked latch comparators. It has been demonstrated that hysteresis is not only sensitive to the clock frequency, but also to several design parameters including the transistors sizes, the common mode input voltage and the tracked input frequencies. The analysis results are validated through electrical simulations using a commercially available 0.18$\mu$m CMOS technology showing a maximum error of 8.6%.

A coplanar waveguide (CPW)-fed I-shaped monopole antenna with independent frequency control characteristic is presented for simultaneously satisfying the global positioning system (GPS), wireless local area network (WLAN), and worldwide interoperability for microwave access (WiMAX) applications. It is printed on an FR4 substrate with a single-layered metallic structure and the overall dimensions are $45\times 25\times 1.6$mm³. The proposed antenna consists of an I-shaped monopole, a pair of split-ring resonators (SRRs), and a coplanar ground plane. The unique advantage of this study is that the four frequency bands are generated individually by different radiating elements. That is, each of them can be controlled independently with little interference from others, which brings added convenience to the antenna design, optimization and debugging processes. Simulated and measured results both demonstrate that it can cover the 1.575GHz GPS (1.57–1.59GHz); 2.4/5.2/5.8GHz WLAN (2.4–2.485, 5.15–5.35 and 5.725–5.825GHz) and 3.5/5.5GHz WiMAX (3.40–3.60 and 5.25–5.85GHz) applications with satisfactory radiation patterns and acceptable gains.

With the increasing power densities, managing the on-chip temperature has become an important design challenge, especially for hard real-time systems. This paper addresses the problem of minimizing the peak temperature under hard real-time constraints using a combination of dynamic voltage scaling and dynamic power management. We derive a closed-form formulation for the peak temperature and provide a genetic-algorithm-based approach to solve the problem. Our approach is evaluated with both simulations and real measurements with an Intel i5 processor. The evaluation results demonstrate the effectiveness of the proposed approach compared to related works in the literature.

Modern mobile devices suffer from severe power and thermal issues due to the adoption of high-frequency multi-core processors. However, methods of resolving the thermal problems in mobile environments are restricted due to their size, semiconductor process technology, and battery limitations. Mobile devices generally rely on a software framework called the Thermal Management Model (TMM). However, conventional TMMs suffer from inevitable performance degradation due to the thermal response. We propose a new Thermal Mitigation Algorithm (TMA) to optimize performance and thermal mitigation by considering the multi-core power curve of a mobile CPU which is experimentally derived using a typical smartphone and thus resolve this issue. Our proposed scheme aims to reduce thermal problems and enhance system performance by limiting the usage of power-inefficient frequencies when operating on a multi-core. We evaluate the proposed algorithm on a real system using a typical smartphone and conduct the performance measurement using the AnTuTu benchmark v4.5.1. In addition, we use the on-chip temperature sensors of CPU cores and a crystal oscillator embedded in the Application Processor (AP) to monitor the temperature of the mobile device. The result shows that our scheme, respectively reduce the average temperatures of CPU cores and a crystal oscillator by 6.61% and 5.02% while improving system performance by 3.24%. In conclusion, we reduce the thermal problems and enhance performance simultaneously using the proposed TMA.

The lifetime of battery-operated sensor platforms (i.e., sensor nodes) is a critical issue. The replacement of their batteries is quite a challenging task if these platforms are deployed for detecting events in inaccessible geographical areas (e.g., forest). This paper describes an optimized RF energy harvester/scavenger (consisting of an antenna, impedance matching circuit and rectifier) for energizing low-power sensor platforms (electronic systems). Few nonmatched rectifiers (using HSMS-285X Schottky diodes) are fabricated to characterize the input impedance for different sets of parameters. After characterization a proper impedance matching circuit is integrated for the maximum power transfer from antenna to rectifier. It is shown that a single stage of RF rectifier is enough to produce output voltage of 1.8V. Very few realizations of RF energy harvester are reported in the literature under 2.4GHz ISM band category. Furthermore, high-gain microstrip patch array antennas are fabricated to capture the maximum power from the surroundings. The maximum harvesting range of 0.92m is obtained at 27dBm transmitting power level.

A novel multiple-output dual-X current conveyor transconductance amplifier with buffer-based square/triangular wave generator is introduced in the paper. The proposed generator provides square wave in current mode and triangular wave in voltage mode. Outputs as square and triangular waves are available from terminals with appropriate impedance levels thereby making the proposed generator circuit easily cascadable in both current and voltage modes. The oscillation frequency and amplitude of output square wave are electronically and independently controllable. One more interesting feature of the proposed generator circuit is the adjustable duty cycle. The proposed circuit of square/triangular wave generator is verified through the HSPICE simulation results carried using 0.18$\mu$m CMOS technology. The simulation results show linear variation of duty cycle against external DC current over a range of 6.5–96%. The variation of square wave’s amplitude via bias current is found to be linear from 10$\mu$A to 80$\mu$A. Moreover, the proposed generator can operate very well up to 23.8MHz with nonlinearity less than 5%. The proposed generator circuit is also experimentally verified.

The hardware-based dictionary compression is widely adopted for high speed requirement of real-time data processing. Hash function helps to manage large dictionary to improve compression ratio but is prone to collisions, so some phrases in match search result are not true matches. This paper presents a novel match search approach called dual chaining hash refining, which can improve the efficiency of match search. From the experimental results, our method showed obvious advantage in compression speed compared with other approach that utilizes single hash function described in the previous publications.