Journal of Circuits, Systems and Computers

A novel area-efficient switching scheme is proposed for the successive approximation register (SAR) analog-to-digital converters (ADCs). The capacitor-splitting structure, charge-average switching technique, and $V_{\mathrm{\text{aq}}}$ (equal to $V_{\mathrm{\text{REF}}}$/4) are combined together and optimized to realize the proposed switching scheme. $V_{\mathrm{\text{aq}}}$ is only used in the last two bit cycles, which affects the ADC accuracy little and reduces capacitor area by half. It achieves a 98% less switching energy and an 87.5% less capacitor area compared with the conventional switching method. In addition, the DAC output common-mode voltage is approximately constant. Thus, the proposed switching method is a good tradeoff among power consumption, capacitor area, DAC output common-mode voltage, and ADC accuracy. The proposed SAR ADC is simulated in 0.18$\mu$m CMOS technology with a supply voltage of 0.6V and at a sampling rate of 20kS/s. The signal-to-noise-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 58.2 and 73.7dB, respectively. The effective number of bits (ENOB) is 9.4. It consumes 42nW, resulting in a figure-of-merit (FoM) of 3.11 fJ/conversion-step.

As single-carrier frequency division multiple access (SC-FDMA) is used in long-term evolution (LTE) uplink communications, high peak-to-average power ratio (PAPR) increases power consumption in mobile devices. It is severe when localized subcarrier mapping is used with higher-order modulations. Companding is an attractive technique that offers a tradeoff between PAPR and bit error rate (BER) performances. This paper proposes an exponential companding technique that uses two companding levels based on a threshold, to reduce PAPR in SC-FDMA systems. It does not increase the average power level of transmitted signal and maintains the BER level without significant degradation from the original system. The proposed scheme has three parameters that can be adjusted for a tradeoff between PAPR, BER, and power spectral density (PSD) performances. Hence it offers more flexibility than the conventional exponential companding scheme. We also present scatter plots to find the optimum threshold value and companding levels. Finally, we verify the proposed technique considering a real-time indoor channel by using a wireless open-access research platform (WARP).

This research paper presents a new evolutionary technique named vortex search optimization (VSO) to design digital 2D finite impulse response (FIR) filter for improved performance both in pass-band and stop-band regions. Optimum filter coefficients are calculated by minimizing the deviation of actual frequency response from specified or desired response. Efficiency of the designed filter is measured by several parameters, such as maximum pass-band ripple, maximum stop-band ripple, mean attenuation in stop band and time taken, to execute the code. Analysis of the performance of designed filter is correlated with various different algorithms like real coded genetic algorithm, particle swarm optimization, genetic search algorithm and hybrid particle swarm optimization gravitational algorithm. Comparative study shows significant reduction in pass-band error, stop-band error and execution time.

In this paper, multi-resolution analysis of two edge-texture based descriptors, Discriminative Robust Local Binary Pattern (DRlbp) and Discriminative Robust Local Ternary Pattern (DRltp), are proposed for the determination of mammographic masses as benign or malignant. As an extension of Local Binary Pattern (LBP) and Local Ternary Pattern (LTP), DRlbp and LTP-based features overcome the drawbacks of these features preserving the edge information along with texture. With the hypothesis that multi-resolution analysis of these features for different regions related to mammaographic masses with wavelet transform will capture more discriminating patterns and thus can help in characterizing masses. In order to evaluate the efficiency of the proposed approach, several experiments are carried out using the mini-MIAS database where a 5-fold cross validation technique is incorporated with Support Vector Machine (SVM) on the optimal set of features obtained via stepwise logistic regression method. An area under the receiver operating characteristic (ROC) curve ($A_z$ value) of 0.96 is achieved with DRlbp attributes as the best performance. The superiority of the proposed scheme is established by comparing the obtained results with recently developed other competing schemes.

Most of the existing peer-to-peer (P2P) content distribution schemes carry out a random or rarest piece first content dissemination procedure to avoid duplicate transmission of the same pieces of data and rare pieces of data occurring in the network. This problem is solved using P2P content distribution based on network coding scheme. Network coding scheme uses random linear combination of coded pieces. Hence, the above-stated problem is solved easily and simply. Our proposed mechanism uses network coding mechanism in which several contents having the same message are grouped into different groups and coding operation is performed only within the same group. The interested peers are also divided into several groups with each group having the responsibility to spread one set of contents of messages. The coding system is designed to assure the property that any subset of the messages can be utilized to decode the original content as long as the size of the subset is suitably large. To meet this condition, dynamic smart network coding (DSNC) scheme is defined which assures the preferred property, then peers are connected in the same group to send the corresponding message, and connect peers in different groups to disseminate messages for carrying out decoding operation. Moreover, the proposed system is readily expanded to support topology change to get better system performance further in terms of reliability, link stress and throughput. The simulation results prove that the proposed system can attain 20–25% higher throughput than existing systems, good reliability, link failure and robustness to peer churn.

The ultimate aim of a memory designer is to design a memory cell which could consume low power with high data stability in the deep nanoscale range. The implementation of Very Large-Scale Integration (VLSI) circuits using MOSFETs in nanoscale range faces many issues such as increasing of leakage power and second-order effects that are easily affected by the PVT variation. Hence, it is essential to find the best alternative of MOSFET for deep submicron design. The Carbon Nanotube Field Effect Transistor (CNTFET) can eradicate all the demerits of MOSFET and be the best replacement of MOSFET for nanoscale range design. In this paper, a 10T CNTFET Static Random Access Memory (SRAM) cell is proposed. The power consumption and Static Noise Margin (SNM) are analyzed. The power consumption and stable performance of the proposed 10T CNTFET SRAM cell are compared with that of conventional 10T CNTFET SRAM cell. The power and stability analyses of the proposed 10T and conventional 10T CNTFET SRAM cells are carried out for the CNTFET parameters such as pitch and chiral vector ($m,n$). The power and SNM analyses are carried out for $\pm$20% variation of oxide thickness (Hox), different dielectric constant (Kox). The supply voltage varies from 0.9V to 0.6V and temperature varies from 27^∘C to 125^∘C. The simulation results show that the proposed 10T CNTFET SRAM cell consumes lesser power than conventional 10T CNTFET SRAM cell during the write, hold and read modes. The write, hold and read stability of the proposed 10T CNTFET SRAM cell are higher as compared with that of conventional 10T CNTFET SRAM. The conventional and proposed 10T SRAM cells are also implemented using MOSFET. The stability and power performance of proposed 10T SRAM cell is also as good as conventional 10T SRAM for MOSFET implementation. The proposed 10T SRAM cell consumes lesser power and gives higher stability than conventional 10T SRAM cell in both CNTFET and MOSFET implementation. The simulation is carried out using Stanford University 32nm CNTFET model in HSPICE simulation tool.

This paper presents a scheme for the modified chaotic circuits based on inductance integration. In view of the fact that the DC resistance of an inductor in the circuit cannot be ignored, this way of constructing the circuits is provided that can eliminate its influence on the integral circuits. By means of cascading an inverting adder circuit and inductance integral circuit, the output signal of the integral circuit is fed back to the inverting adder circuit, and its additive term is artificially added to match the actual inductance integrated circuit to achieve integral circuit based on the actual inductor which can offset the effect of its DC resistance. In order to verify the generality of the design, the process of designing Lorenz chaotic circuit is given and its attractors can also be observed from the oscilloscope.

This paper presents a highly-integrated transceiver with a differential structure for C-band (5–6GHz) radar application using a switchless and baluns-embedded configuration. To reduce the noise figure (NF) in receiver (Rx) mode and enhance the output power in transmitter (Tx) mode, the balun at RF port is embedded into the low-noise amplifier (LNA) and the power amplifier (PA), respectively. Besides, the RF switch is removed by designing the matching networks that both LNA and PA can share. The same topology is also adopted at the IF port. To achieve a high image rejection ratio (IRR), a Hartley architecture using polyphase filters (PPFs) is adopted. The proposed transceiver has been implemented in 1P6M 0.18-$\mu$m CMOS process. The receiver achieves 6.9-dB NF, $-$7.5-dBm IIP₃ and 26.3-dB gain with three-step digital gain controllability. Also the measured IRR is better than 41dBc. The transmitter achieves 9.6-dBm output power and 19.2-dB gain. The chip consumes 106mA in the Rx mode and 141mA in the Tx mode from the 3.3-V power supply.

In this paper, we propose an oscillation-type transceiver for wireless chip-to-chip communication (WCC). The proposed transceiver is composed of a ring oscillator, coils, inverter-type amplifier, voltage multiplier and comparator. The ring oscillator itself acts as the on–off keying (OOK) modulator. The envelope of the transferred OOK-modulated signal is detected in the voltage multiplier of the receiver. Given that the proposed transceiver uses an OOK-modulated oscillating signal, the noise immunity is improved compared to the typical pulse-type transceiver. To verify the functionality of the proposed transceiver, we design the transceiver using the 180-nm complementary metal-oxide-semiconductor process. From the measured results, we verify that the proposed transceiver recovers the entered digital signal up to a distance of 0.2mm between the primary and secondary coils. Additionally, the sensitivity to the bias voltage of the latch is nonexistent by virtue of removing the latch in the proposed transceiver.

This paper introduces an electronically tunable mixed-mode universal biquad filter configuration employing four single output operational transconductance amplifiers (OTAs), one dual output OTA and two grounded capacitors (GCs) (ideal for integrated circuit implementation and absorbing shunt parasitic capacitances). The presented structure can realize all second-order filter functions, namely, low pass (LP), high pass (HP), band pass (BP), band reject (BR) and all pass (AP) responses in voltage mode (VM), current mode (CM), transresistance mode (TRM) and transconductance mode (TCM) using appropriate selection(s) of input signals. The cut-off frequency ($f_o)$ and bandwidth (BW) of the realized filters can be tuned orthogonally through the transconductance (by varying the bias currents) of the OTAs. The proposed biquad configuration enjoys low active and passive sensitivities. The workability of this multifunctional biquad filter topology has been confirmed through simulations using MATLAB and Analog Design Environment (ADE) spectre tool provided by Cadence Virtuoso, using 0.18$\mu$m CMOS process parameter. The post-layout simulations have also been carried out to validate the theory.

Wireless sensor networks (WSNs) comprise a large number of tiny sensing nodes, which are battery-powered with limited energy. An energy-efficient routing protocol is of utmost importance to prolong the network lifetime. Clustering is the most common technique to balance energy consumption among all nodes, while minimizing traffic and overhead during the data transmission phases. In this paper, a Multi-Objective nature-inspired algorithm based on Shuffled frog-leaping algorithm and Firefly Algorithm (named MOSFA) as an adaptive application-specific clustering-based multi-hop routing protocol for WSNs is proposed. MOSFA’s multi-objective function regards different criteria (e.g., inter- and intra-cluster distances, the residual energy of nodes, distances from the sink, overlap, and load of clusters) to select appropriate cluster heads at each round. Moreover, another multi-objective function is proposed to select the forwarder nodes in the routing phase. The controllable parameters of MOSFA in both clustering and multi-hop phases can be adaptively tuned to achieve the best performance based on the network requirements according to the specific application. Simulation results demonstrate average lifetime improvements of 182%, 68%, 30%, and 28% when compared with LEACH, ERA, SIF, and FSFLA, respectively, in different network scenarios.

Using logic gates is the traditional way of designing logic circuits. However, in many cases, the use of modules is advantageous as the module is considered a uniform structure composed of multiple gates. In this paper, a nonlinear approach is proposed for designing logic circuits for use as modules multiplexers (MUXs) or Reed–Muller universal blocks (RMs). The experimental results show that the method gives better results compared to other methods available in the literature. The main advantages of the method are that it guarantees minimality and it can also handle Boolean functions for incompletely specified functions. The method is general enough and can be used for any kind of modules.

With the growing trend towards reducing the size of electronic devices, reducing power consumption has become one of the major concerns of circuit designers, and designing reversible circuits is one of the approaches proposed for reducing power consumption. Although several studies have been done in the field of synthesizing combinational reversible circuits, little work has been done for designing reversible sequential circuits. Furthermore, many researches in this context use traditional designs which replace latches, flip-flops and associated combinational gates with their reversible counterparts. This traditional technique is not very promising, because it leads to high quantum cost (QC) and garbage outputs. Recently, researchers have proposed direct design of reversible sequential circuits using Reed Muller expressions to obtain next state output. Since most sequential circuits have multiple outputs, using common product terms between multiple outputs might decrease QC significantly.

In this paper, a modular and low QC design for a synchronous reversible $n$-bit up/down counter with parallel load capability is presented. In this design, the common terms among multiple outputs are used efficiently, which leads to a low QC for the counter. A general formula to evaluate the QC of our proposed reversible counter is presented. This result shows that in our proposed design by increasing the number of bits of counter ($n)$, the QC increases linearly, while in previous works by increasing the number of bits of counter, the QC increases exponentially.

In this paper, the principles, the design, the methodology of low cost implementation and the results of implementation of a shunt active power filter (SAPF) in the embedded system environment are presented. The system for which the SAPF is considered has a combination of linear reactive load and a three-phase-fed diode bridge rectifier that drives an RL load. The generation of the compensating signal or the reference signal is based upon the direct calculations implemented using the linear operational amplifiers. Further, the generation of the pulse width modulation (PWM) pulses is much similar to the conventional sinusoidal PWM but implemented in the embedded system platform. In this work, the built-in PWM and ADC sections of the microcontroller PIC 16F877A have been utilized for generating the PWM pulses without the requirement of an explicit carrier signal. The proposed method has been validated in MATLAB SIMULINK environment and also by an experimental prototype.

Most popular scientific workflow systems can now support the deployment of tasks to the cloud. The execution of workflow on cloud has become a multi-objective scheduling in order to meet the needs of users in many aspects. Cost and makespan are considered to be the two most important objects. In addition to these, there are some other Quality-of-Service (QoS) parameters including system reliability, energy consumption and so on. Here, we focus on three objectives: cost, makespan and system reliability. In this paper, we propose a Multi-objective Evolutionary Algorithm on the Cloud (MEAC). In the algorithm, we design some novel schemes including problem-specific encoding and also evolutionary operations, such as crossover and mutation. Simulations on real-world and random workflows are conducted and the results show that MEAC can get on average about 5% higher hypervolume value than some other workflow scheduling algorithms.

The watermarking technique is an active subject in current research used as a solution for copyright protection in multimedia documents. In this paper, we propose the first hardware invisible robust video watermarking application based on motion estimation. Since the designers of this application face many challenges, two types of architecture are performed: static and dynamic/partial reconfigurable architecture. The proposed architecture is adapted to HEVC encoded video. Two protection techniques are linked up: the digital watermarking to insert a watermark in the video, and the scrambling technique for overall video protection. The watermark embedding is treated in the horizontal and vertical components of even motion vectors. Eventually, the entire vectors are scrambled. The used watermark is a binary sequence where only one bit is inserted into the horizontal and the vertical components of motion vectors. The recommended architecture applies for slow and fast video sequence, where we use a motion estimator reconfigured according to the macro-block video movement. We also utilize a pipeline structure and a clock gating module to increase computing power and reduce power consumption. Experimental results show that the suggested static and dynamic/partial reconfigurable architecture guarantees material efficiency and superior performance in terms of frequency and power consumption.

In this paper, we present a novel, almost-digital approach for bolometer readout circuits to overcome the area and power dissipation bottlenecks of analog-based classical microbolometer circuits. A current-controlled oscillator (CCO)-based analog-to-digital converter (ADC) is utilized instead of a capacitive transimpedance amplifier (CTIA) in the classical readout circuits. This approach, which has not been reported before, both produces the required gain in the bolometer input circuit and directly digitizes the bolometer signal. With the proposed architecture, the need for large capacitances (of the order of 10–15pF for each column) at which the current is accumulated in the bolometer circuits and the voltage headroom limitation of classical microbolometer circuits are eliminated. Therefore, the proposed architecture permits to design readout circuits with reduced pixel pitch and lower power supply, both of which in turn lead to higher-resolution Focal Plane Arrays (FPAs) with lower power dissipation. The new architecture is modeled and simulated using a 180-nm CMOS process for sensitivity, noise performance, and power dissipation. Unlike the 3.3-V power supply usage of classical readout circuits, the proposed design utilizes 1.2-V analog and 0.9-V digital supply voltages with a power dissipation of almost half of the classical approach.

Electroencephalography (EEG) is the recording of electrical activity of the brain. The 10–20 system is the standard electrode location method used to acquire EEG data, which uses 21 electrodes to record the electrical activity of the brain. Patient preparation and correct electrode placement are important to obtain reliable outputs. The current 10–20 system consumes greater time for patient preparation and also causes discomfort due to a higher number of electrodes being used or wearing an uncomfortable cap. This paper focuses on reducing the number of electrodes, thus reducing patient discomfort as well as preparation time. Advancement in the field of hardware and software processing has led to the utilization of brain waves for communication between human and the computer. This work deals with EEG-based Brain–Machine Interface (BMI) intended for designing a portable single-channel EEG signal acquisition system. EEG signal was acquired using the data acquisition module [National Instruments (NI) myDAQ] and the signal was viewed in the NI Laboratory Virtual Instrument Engineering Workbench (LabVIEW) environment. It was observed that the peak-to-peak amplitude of alpha, beta and theta waves changes in accordance with the activity the subjects performed. Thus, the developed instrument was tested on 10 different subjects to acquire the alpha, beta and theta waves by performing different activities. From the results, it can be concluded that the developed system can be used for studying a person’s brain waves (alpha, beta and theta) based on the activity performed by the subject with a limited number of electrodes.

Due to chip manufacturing process defects and other factors, the virtual channel permanent fault may occur at the wireless interface in the WiNoC. This fault will affect the operating efficiency of the wireless router and degrade the network performance of the chip. In order to effectively tolerate permanent faults in virtual channels, faults are subdivided into coarse-grained and fine-grained faults. When a fine-grained fault of the virtual channel occurs at the wireless interface, the remapping mechanism is used to tolerate it; when a coarse-grained fault occurs, this unavailable virtual channel is directly abandoned and permanent fault information is broadcast to all nodes in the network. Packets that require a wireless channel can be routed to avoid passing through the fault wireless router. This method can effectively reduce the routing delay caused by the permanent fault of the virtual channel at the wireless interface. Experiments show that compared with the traditional WiNoC and other WiNoC fault-tolerant schemes, the fault-tolerant scheme proposed in this paper has a great improvement in performance and the advantages of low overhead and good scalability.