Journal of Circuits, Systems and Computers

Assisted Reproductive Technology (ART) is a set of medical procedures primarily used to address infertility. Success Rate of ART is very low because it is affected by large number of variables. Machine Learning Techniques are now applied to predict ART outcome and to find strategies to improve success rate. For this, determining the best performing classifier for ART is very important. Previously, some classifiers are applied to ART with static data. But, in reality, the datasets are dynamic in nature and require dynamic setup which can be achieved with the help of Incremental Classifiers. Due to low success rate, the ART dataset contains less number of records for positive results that make the dataset imbalanced. This research work first finds the best evaluation metric for classification on imbalanced dataset and then balances the dataset using three different balancing techniques such as undersampling, oversampling and Synthetic Minority Oversampling Technique (SMOTE) and applies five different Incremental Classifiers, namely Stochastic Gradient Descent (SGD), Stochastic Primal Estimated sub-GrAdient SOlver for Support vector machine (SPegasos), Naïve Bayes Updatable, Instance Based (IBk), Averaged One Dependence Estimators (A1DE) Updatable and finds the best balancing technique and suitable classifier for ART outcome prediction. The result shows that for an imbalanced dataset Receiver Operating Characteristics (ROC) Area may be taken as a metric instead of the accuracy. It is found that SMOTE is best method for balancing the ART dataset and IB1 classifier performs well for the balanced data with the high prediction rate of 92.3 for ROC. Finally, various Feature Selection methods are applied to the top three best performing classifiers and suitable feature selection method for each classifier is identified.

Block scheduling is difficult to implement in P2P network since there is no central coordinator. This problem can be solved by employing network coding technique which allows intermediate nodes to perform the coding operation instead of store and forward the received data. There is a general assumption in this area of research so far that a target download rate is always attainable at every peer as long as coding operation is performed at all the nodes in the network. An interesting study is made that a maximum download rate can be attained by performing the coding operation at relatively small portion of the network. The problem of finding the minimal set of node to perform the coding operation and links to carry the coded data is called as a network code minimization problem (NCMP). It is proved to be an NP hard problem. It can be solved using genetic algorithm (GA) because GA can be used to solve the diverse NP hard problem. A new NCMP model which considers both minimize the resources needed to perform coding operation and dynamic change in network topology due to disconnection is proposed. Based on this new NCMP model, an effective and novel GA is proposed by implementing problem specific GA operators into the evolutionary process. There is an attempt to implement the different compositions and several options of GA elements which worked well in many other problems and pick the one that works best for this resource minimization problem. Our simulation results prove that the proposed system outperforms the random selection and coding at all possible node mechanisms in terms of both download time and system throughput.

In the class of the boost converters, the conventional DC–DC boost converters are in common practice but their limited boost capabilities at higher duty ratios are one of the concerns. The isolated and non-isolated step-up DC–DC converters are one of the remedies of the above issue. The presence of switched inductor and switched capacitors in the circuit of non-isolated configuration can provide considerable step-up in voltage at the output, and also facilitate lower voltage stress on components. In this paper, work has been done to propose three non-isolated high-voltage gain DC–DC boost converter topologies. Along with the high voltage gain, the topologies also have lesser voltage stress across the active power switches and diodes used in topologies. The proposed topologies are suitable for low dc input levels like renewable sources, microgrid and grid-connected applications. A Matlab/Simulink 2017a environment is utilized to derive, design and simulate the proposed topologies for a 100-W load operation. The basic topology is also realized in hardware as a prototype circuit with 100-W resistive load, operated at 50kHz switching frequency.

Reversible circuits have been extensively investigated because of their applications in areas of quantum computing or low-power design. A reversible circuit is composed of only reversible gates and allow computations from primary inputs to primary outputs and vice-versa. In the last decades, synthesis of reversible circuits received significant interest. Additionally, testing of these kinds of circuits has been studied which included different fault models and test approaches dedicated for reversible circuits only. The analysis of testability issues in a reversible circuit commonly involves the detection of the missing gate faults that may occur during the physical realizations of the reversible gates. In this paper, we propose a design for testability (DFT) technique for reversible circuits in which the gates of a circuit are clustered into different sets and the gates from each cluster are then connected to an additional input line where, the additional line acts as an extra control input to the corresponding gate. Such arrangement makes it possible to achieve $100\%$ fault detection in any reversible circuit with a small increase in quantum cost. Experimental evaluations confirm that the proposed DFT technique incurs less quantum cost overhead with $100\%$ fault detection compared to existing DFT techniques for reversible circuits.

Orthogonal Frequency Division Multiplexing is a multi-carrier modulation technique which provides numerous advantages like high spectral efficiency, minimal interference, low multipath fading, etc. But Peak-to-average Power Ratio is a severe challenge in using such multiplexing technique as it introduces distortions in nonlinear devices. Various Peak-to-average Power Ratio reduction techniques have been investigated in the literature to improve the performance of Orthogonal Frequency Division Multiplexing systems. But, each of them suffers either from high complexity or degraded bit error rate or less spectral efficiency. For reducing Peak-to-average Power Ratio more effectively, a hybrid combination of Partial Transmit Sequence with Selective Mapping is detected to show better performance. In this paper, we have combined Goppa coding technique with this hybrid Selective Mapping and Partial Transmit Sequence for further improving the performance. Along with Peak-to-average Power Ratio reduction capability, the proposed technique also has inherent error control mechanism due to the use of coding. Based on the simulation results, we have concluded that the proposed technique provides good amount of Peak-to-average Power Ratio reduction than conventional techniques. The proposed technique is analyzed for different number of Orthogonal Frequency Division Multiplexing symbol candidates for Selective Mapping and different number of block divisions for Partial Transmit Sequence. Further, this technique is simulated for different number of subcarriers and modulation order and the simulation results are compared with each other. The proposed technique also shows better Bit error rate values for high Signal-to-Noise ratio.

Recently, a variety of different machine learning methods improve the applicability of activity recognition systems in different scenarios. For many current activity recognition models, it is assumed that all data are prepared well in advance and the device has no storage space limitation. However, the process of the sensor data collection is dynamically changing over time, the activity category may be continuously increasing, and the device has limited storage space. Therefore, in this study, we propose a novel class incremental learning comprehensive solution towards activity recognition with knowledge distillation. Besides, we develop the representative sample selection method to select and update a specific number of preserved old samples. When new activity classes samples arrive, we only need the new classes samples and the representative old samples to preserve the network’s performance for old classes while identifying the new classes. Finally, we carry out experiments using two different public datasets, and they show good accuracy for old and new categories. Besides, the method can significantly reduce the space required to store old classes samples.

In the coal-fired power generation system, it is necessary to predict the NO_x emissions of power station boilers when it comes to the step to spray ammonia to ensure that NO_x emissions do not exceed national standards. Using traditional machine learning algorithms in the modeling of power station boilers will require features selection and steady-state extraction, which is not suitable for practical applications. In order to reduce the NO_x prediction error rate under variable operating conditions, a multi-model fusion algorithm S3LX combined with linear regression, XGBoost, and long-short-term memory recurrent neural network is proposed to model the NO_x emission prediction of power station boilers. The preprocessing data scheme suitable for power station boiler data sets is proposed and implemented in this paper, which can perform numerical processing, data cleaning and data standardization for boiler’s data and features. A 7-day historical operating data set of a unit in Guangzhou Shajiao C Power Plant was used as the training set and test set and was used to build the NO_x emission prediction model after data preprocessing. Results show that compared with traditional machine learning algorithms, S3LX has good prediction ability under varying conditions with an average error of 4.28%. Compared with the average prediction error of the multi-layer perceptron 9.16%, SVM 7.37%, S3LX makes the error significantly reduced and satisfies the actual engineering demand.

This study manifests a fuzzy-based trust prediction model for detecting malicious nodes in wireless sensor networks (WSN) by preventing black hole attack. Besides, a new routing protocol based on the shortest path and trust to the path nodes is presented with a fuzzy estimator, which uses the data mining methods to detect the malicious nodes (black holes). In a black hole attack, a malicious node selects the RREP (Route Replay) message as the shortest path from the source node to the destination node. After that, the packet sent to the malicious node is not received by the network. Eventually, the malicious node releases the entire data packet instead of sending it to the destination node. Optimal path selection is performed according to different algorithms on the objective function and its results are observed for route selection. After defining the objective function, different algorithms such as Genetic Algorithm (GA) and teaching–learning-based optimization (TLBO) are utilized for routing. For each algorithm, the objective function for the most secure node is evaluated and simulated based on the parameters defined in fuzzy logic. Based on the simulation results under MATLAB software, TLBO algorithm has obtained the best response for path selection with the least cost for the target performance. Significantly, the proposed method is simple and based on the exchange of control packets between the sensor node and the base station. In accession, the results show that the proposed algorithms are effective in detecting and preventing black hole attacks.

Object tracking is a hot topic in computer vision. The significantly developed satellite video technology makes object tracking in satellite videos possible. In recent years, Convolutional Neural Network (CNN)-based trackers have achieved satisfying performance in the visual object tracking field. However, CNN cannot be directly applied to object tracking in satellite videos due to the following two reasons. First, the feature map size generally decreases as the network layer deepens, which is unsuitable for the small targets in satellite videos. Second, CNN-based trackers commonly need extensive data to train the network parameters, while few labeled satellite videos are available. Therefore, in this paper, we design a lightweight network for the satellite video tracking task. On one hand, the network generates a response map with the same size as the input image and reserves the spatial resolution of targets. On the other hand, the network parameters are transferred from an existing network and trained with the initial annotated frame, thus no extra data are needed. To make a fair comparison between existing trackers, we further propose a simulated benchmark based on the UAV123 dataset according to the imaging characteristics of satellite videos. Experiments are conducted to compare our method with other state-of-the-art trackers on both the simulated benchmark and real satellite videos and experimental results demonstrate the superiority of our proposed algorithm.

Numerous empirical studies show that portfolio returns are generally asymmetric, and investor would prefer a portfolio return with larger degree of asymmetry along with risk and return. In this paper, a concept of skewness is defined as the third central moment and studied its mathematical properties. To predict the stock prices, a novel recurrent neural network with gated recurrent unit (GRU) cell is preferred. Based on these predictions, stock returns, entropic value at risks and skewness are calculated. A mean–EVaR–skewness multi-objective portfolio optimization model is devised to account for market uncertainty. Cardinality, bounding restrictions, and liquidity are considered in addition to risk and return to make the model more effective. Uncertain goal programming is used to solve the proposed model. Finally, an example portfolio is presented to display the efficacy and the feasibility of the model suggested in this paper.

This paper presents two novel current-mode Full Adders based on Carbon Nanotube FET (CNFET). They comprise of three main parts: current-to-voltage converter, threshold detector and voltage-to-current converter. While other designs in the literature use either inverter or current source for detecting threshold, the new designs are based on a heuristic usage of an Ultra Low-Power Diode (ULPD) as voltage regulator. The use of diode does not lengthen the critical path and thereby ensuring high-speed operation. It does not increase power consumption significantly either. Simulation results by HSPICE and 32nm CNFET technology file demonstrate at least 19% higher performance in terms of energy consumption for the second proposed Full Adder compared to other traditional and state-of-the-art current-mode and mixed-mode designs.

Storage of data security has emerged as a basic necessity for both large- and small-scale industries. Cloud computing is internet-based computing technology in which people can work with their application with a high level of security in Internet of Things (IoT) enhanced devices. Cloud computing also provides privilege to store data that are collected from the devices in server side. Confidentiality and integrity of data play a major issue in cloud computing while preserving the IoT data. In this paper, the security of data is achieved by performing clustering and further applying cryptographic technique to the clustered data gathered from the devices that connected to the internet. Security of data can be improved by using a prominent cryptographic technique Attribute Based Encryption (ABE). Initially, the documents are clustered using the EM algorithm and clustered results are stored in various parts of the cloud. These documents are secured and can be accessed by the user who satisfies the attributes. In some cases, if the users’ attributes are not satisfied with the documents, it cannot be accessed by the corresponding user. Thus, the data from various devices are encrypted and maintained by the owner securely.

A newly proven technique is non-invasive bio-impedance, and also known as Electrical Impedance Tomography (EIT), which is used for medical or non-medical applications. EIT images are based on the internal distributions of the conductivity or resistivity from the boundary data, which depend on the voltage measurement of the stomach attached electrodes of the human body. An experimental study of the EIT system presented here has been used 8/16 surface electrodes configurations for the human body’s stomach. Then, according to the data acquisition methods of the EIT, the surface potentials of the stomach through the current injection were measured. For current pulses, a voltage-controlled current source has been created, and the created current source is a combination of voltage to current converter and current signal generator. Current positions and measuring voltages have been calculated using the designed control unit. However, the imaging algorithm requires sufficient data through the experimental work, which defines the cross-sectional image of resistivity. The cross-sectional image has been based on the Finite Element Method (FEM). It produces 2D/3D images, impedance distribution graphs and Mesh models. The proposed EIT system has been used for non-medical and industrial applications, which have non-invasive, inexpensive, radiation-free and a high potential for imaging modality.

In this paper, an Ultra-Wideband (UWB) low noise amplifier (LNA) with low power consumption and high-power gain in 180nm CMOS technology is presented. An innovative combination of conventional methods to design UWB-LNA, i.e., resistive-feedback, inductive-series peaking, noise cancelling and inductive degeneration techniques is described here. The proposed LNA consists of two common source amplifiers with resistive feedback in which the noise and power consumption have been reduced by using the noise cancelling and current reuse techniques, respectively. Also, resistive feedback in the first stage reduces input resistance, hereby improving input impedance matching. In the second stage, which is used to increase the power gain, a common source structure with inductive-series peaking and noise cancellation techniques is used. The analytical results agree well with the post layout simulation results. The post-layout simulation shows a gain of $19\pm 1.5$dB and noise figure (NF) of 2.3dB in the whole $-3$dB bandwidth of 0.1GHz to 6.1GHz, while the S11 and S22 are less than $-11$dB. The proposed circuit has a figure of merit of 9.9 which is significantly improved compared to the previous works. The total power dissipation is only 7.3mW, and the active area is less than 0.7mm².

In real life, the increased data accessing speed and data storage ability is required by most of the machinery fields. However, the real-world problems can be studied effectively with the combination of scientific computational techniques with the mathematical models. Automata theory is known to be the popular mathematical model. Towards most of the software and hardware related applications, the computational methods are analyzed and designed using significant automata theory concepts (likely, pushdown automata (PDA), Turing machines (TMs) and finite automata (FA)). Hence, the conventional lecture-driven style has attracted the reflective preferences of learners using these abstract natured concepts. But the lecture-driven teaching style has less motivated the computer engineering learners. In order to learn automata theory and computational models, we introduce the PDA and TM in a virtual platform. However, this work has motivated the improvement of longitudinal experimental validation and learning using the modern technology. Java Formal Languages and Automata Package (JFLAP) tool is used to write our simulators in JAVA language and the results are obtained from each machine through simulating the input strings.

In the proposed work, a differential write and single-ended read half-select free 12 transistors static random access memory cell is designed and simulated. The proposed cell has a considerable reduction in power dissipation with better stability and moderate performance. This cell operates in subthreshold region and has a higher value of read static noise margin as compared to conventional six transistors static random access memory cell. A power cut-off technique is utilized between access and pull-up transistors during the write operation. It results in an increase in write static noise margin as compared to all considered cells. In the proposed cell, read and write access time is improved along with a reduction in read/write power dissipation as compared to conventional six transistors static random access memory cell. The bitline leakage current in the proposed cell is reduced which improves the $I_{\mathrm{\text{on}}}/I_{\mathrm{\text{off}}}$ ratio of the cell under subthreshold region. The proposed cell occupies less area as compared to considered radiation-hardened design 12 transistors static random access memory cell. The computed electrical quality metric of proposed cell is better among considered static random access memory cells. Process variation analysis of read stability, access time, power dissipation, read current and leakage current has been performed with the help of Monte Carlo simulation at 3,000 points to get more soundness in the results. All characteristics of static random access memory cells are compared at various supply voltages.

A simple analog multiplier circuit employing one current-mode active building block (ABB) and two n-channel metal-oxide semiconductor (NMOS) transistors is presented in this paper. The used ABB is extra-X second generation current conveyor. The used NMOS transistors are operated in triode region. The circuit has appropriate impedance level at the input and output terminals. Some other key features of the proposed circuit are as follows: suitable to integrated circuit fabrication, good dynamic range and low operating power supplies. The nonideal effects of extra-X second generation current conveyor on the proposed circuit are studied. Additionally, the layout of the proposed circuit is developed using Cadence VIRTUOSO Analog Design Environment with gpdk 0.18$\mu$m technology and post layout simulation results are given to verify the theoretical aspects.

Chip testing is an effective way to reduce the number of defective or faulty chips that reach the market. However, as large-scale test patterns need to be transmitted into a circuit under test during testing, the transmission time dominates the test application time of the chip testing. Therefore, code-based compression methods are widely used in compressing test patterns because of their capability to reduce the transmission time and save storage space significantly. Current code-based compression methods cannot fully apply the inherent characteristics of test patterns yet. To address this problem, this study proposes two-stage test pattern preprocessing algorithms, thereby improving the efficiency of the code-based compression method. First, we propose a column-wise reordering for Hadamard matrix (CRHM) algorithm, which decomposes a test set consisting of test patterns into a primary component set (PCS) and a residual component set (RCS). The PCS inherits some 1s from the original test set (OTS), and other 1s belong to the RCS. As the number of 1s contained in the RCS is less than that in the OTS, the RCS can obtain a higher code-based compression ratio. The PCS can be generated by an on-chip generator, which does not consume transmission time. Second, we propose a novel column-wise reordering for the RCS (CRRCS) algorithm. The CRRCS solves the new location of each column of the RCS one by one in the list to decrease the entropy of the RCS. The entropy denotes the shortest length of the codeword required for the symbol to be encoded. The smaller entropy value refers to a higher compression ratio. For the sorted RCS, more high-frequency symbols can be replaced by shorter codewords. Experimental results based on seven code-based compression methods show that the proposed algorithms can increase the average compression ratio by a total of 19.91%, and the highest average compression ratio reaches 85.04% for ISCAS’89 benchmark circuits.

Generally, cochlear implant system consists of one or more electrodes which directly activate the auditory nerve. The microphone transforms external speech processor input into stimuli for each electrode and transcutaneous the connection between the electrodes and processor. As a result, cochlear implants continue to improve the performance of speech processor. After the implantation, preservation gains importance in acoustic hearing to prevent the neural degradation from the loss of cells. Eventually, the possibility of preserving low-frequency and high-frequency hearing using modified surgical technique has been explored for hearing in cochlear implantation. The primary focus on the architecture is to reduce the major potential thread performance and power trade-off. So, frequency mapping function with modified FIR filter has been proposed. For this implementation, the values relative to the frequency range defines upper and lower stimulus limits of each electrode. The proposed FIR filter is designed with distributed arithmetic function where the reconfigurable FIR filter can change the filter input coefficients. By scaling both the frequency ranges and by assessing the deriving frequency parameters, the mapping function will be yielded. Mapping function is manipulated to rectify any mapping deviations. This results in favor of the development of frequency specific mapping function with flexible system. From the proposed results, it is evident that the speech recognition performance is improved significantly by better minimization of overall energy consumption based on effective and pipelined FFT architecture. This implementation also reduces the power and improves the accuracy by 90% and above for different frequency ranges.

In this paper, a low-power structure as an inverter-base circuit is reported for broadband applications. The focus in this study is in obtaining a low-power structure. By applying cascoded structure to an inverter as a feedforward network in the structure, the DC current and hence the power dissipation are decreased. Also, by adding a two-stage active feedback, which yields no miller capacitance, to the cascoded inverter, the structure of the TIA is completed. Simulation results in HSPICE using 90nm CMOS technology parameters show 41dB$\mathrm{\Omega }$ transimpedance gain, 6.5GHz frequency bandwidth and 2.7$\mu$Arms input referred noise, which consumes only 1.67mw power at 1V supply. Results and analysis indicate that the proposed TIA is suitable to work as a low-power 10 Gbps transimpedance amplifier in an optical receiver.