Journal of Circuits, Systems and Computers

Emergent wireless communication standards, which are employed in different transmission environments, support various modulation schemes. High-order constellations are targeted to achieve high bandwidth efficiency. However, the complexity of the symbol-by-symbol Maximum A Posteriori (MAP) algorithm increases dramatically for these high-order modulation schemes. In order to reduce the hardware complexity, the suboptimal Max-Log-MAP, which is the direct transformation of the MAP algorithm into logarithmic domain, is alternatively implemented. In the literature, a great deal of research effort has been invested into Max-Log-MAP demapping. Several simplifications are presented to meet with specific constellations. In addition, the hardware implementations dedicated for Max-Log-MAP demapping vary greatly in terms of design choices, supported flexibility and performance criteria, making them a challenge to compare. This paper explores the published Max-Log-MAP algorithm simplifications and existing hardware demapper designs and presents an extensive review of the current literature. In-depth comparisons are drawn amongst the designs and different key performance characteristics are described, namely, achieved throughput, hardware resource requirements and flexibility. This survey should facilitate fair comparisons of future designs, as well as opportunities for improving the design of Max-Log-MAP demappers.

This paper introduces the experimental results obtained after processing an electrocardiographic signal by a full-custom, low-complexity, Sigma-Delta Modulator integrated circuit, designed and fabricated using the C5N CMOS technology available through MOSIS. By exploiting a large oversampling ratio, it was possible to obtain an effective number of bits equal to 11 at the proposed single-bit modulator’s output. The resulting bitstream was captured with a logic-state analyzer and processed offline. After decimation and digital filtering, the electrocardiographic signal was reconstructed and plotted in the time domain. Commonly referred quality metrics over the retrieved signal were calculated. A total signal-to-noise and distortion ratio, superior to 66dB, was achieved by analyzing the entire system. The proposed approach shows the feasibility of processing electrocardiographic signals using low-cost and straightforward CMOS technology circuits. Since the proposed converter uses a single voltage supply of 1.5V, exhibits a power consumption of 38$\mu$W, and uses a silicon area of 0.052mm², it is suitable for single battery-operated systems on a chip.

In this paper, we propose a strong spatio-temporal mechanism with correlation filters to solve multi-modality tracking tasks. First, we use the features of the previous four frames as spatio-temporal features, then aggregate the spatio-temporal features into the filters learning and positioning of the adjacent frame. Second, we enhance the temporal and spatial characteristics of the current frame filter by learning the previous four frame filters and spatial penalty. From the experimental results on the GTOT, VOT-TIR2019 and RGBT234 datasets, our strong spatio-temporal correlation filters has achieved excellent performance.

By endowing network with the ability of reliable scheduling of security resources, it can realize the dynamic deployment of security resources as well as the efficient configuration of protection resources, and further can quickly respond to network security threats and emergencies timely. Furthermore, due to the network is increasingly complex, it is of great importance to make it reliable by invoking appropriate security resources. However, the security mechanism and response speed of traditional network based on security domain division, network boundary protection are hard to meet the requirements of the virtual network. In this paper, we propose the SDN-empowered reliable and dynamic scheduling scheme for security resources. In the scheme, we use network security resource virtualization technology to virtualize and modularize network security software and hardware resources; at the SDN control layer, we propose meta-security function combination technology to provide on-demand customization for various security applications’ security service; by using role-based conflict detection and conflict resolution technology, we can detect and handle security rule conflicts. The experiments show that the scheme is reliable and efficient with low latency and great throughput.

This paper introduces an FPGA implementation of a pseudo-random number generator (PRNG) using Chen’s chaotic system. This paper mainly focuses on the development of an efficient VLSI architecture of PRNG in terms of bit rate, area resources, latency, maximum length sequence, and randomness. First, we analyze the dynamic behavior of the chaotic trajectories of Chen’s system and set the parameter’s value to maintain low hardware design complexity. A circuit realization of the proposed PRNG is presented using hardwired shifting, additions, subtractions, and multiplexing schemes. The benefit of this architecture, all the binary multiplications (except $X_i\cdot Y_i$ and $X_i\cdot Z_i)$ operations are performed using hardwired shifting. Moreover, the generated sequences pass all the 15 statistical tests of NIST, while it generates pseudo-random numbers at a uniform clock rate with minimum hardware complexity. The proposed architecture of PRNG is realized using Verilog HDL, prototyped on the Virtex-5 FPGA (XC5VLX50T) device, and its analysis has been done using the Matlab tool. Performance analysis confirms that the proposed Chen chaotic attractor-based PRNG scheme is simple, secure, and hardware efficient, with high potential to be adopted in cryptography applications.

This paper proposes a new watermarking algorithm based on a single-level discrete wavelet transform (DWT). This method initially chooses ‘$l$’ number of carrier frames to hide the data. After estimating the carrier frames, each frame is separated into RGB frames. Each R, G, and B frames are decomposed using a single-level DWT. The horizontal and vertical coefficients are selected to embed the watermark information since small changes in the horizontal and vertical coefficients do not highly affect the quality of the video frame. The watermark image pixels are shuffled using a predetermined key before embedding. The shuffled pixels are converted to binary, and they are grouped into three data matrices. Each data matrix is embedded in horizontal and vertical coefficients of the R, G and B frames of the video frame. After embedding the data, the watermarked video is reconstructed using the original approximation coefficients, the embed coefficients, and the original diagonal coefficients. During the extraction process, the watermark is extracted from the horizontal and vertical coefficients of the watermarked video. Experimental result reveals that the proposed method outperforms other related methods in terms of video quality and structural similarity index measurement.

In this research paper, a simple design of an ultra-wideband (UWB) multi-input multi-output (MIMO) antenna with low envelope correlation coefficient (ECC), high isolation, enhanced gain, radiation efficiency and reconfigurable band notching functionality is proposed. Two symmetrical slots are carefully integrated into the partial ground plane of the conventional monopole to provide a notched band at 5.8GHz for the WLAN system. This notching method is simple and does not endure negative effect performance or any design complexity. The notched band is then controlled using PIN diodes. A complete biasing circuit is integrated on the same partial ground plane to bias the PIN diodes in forward and reverse directions. To reduce the complexity of the design that may be increased due to the reconfiguration circuit, isolation enhancement is accomplished by orthogonal placement of the elements rather than using any additional decoupling structures. A prototype of the MIMO UWB structure is fabricated and its performance parameters are experimentally tested. The captivating agreement between simulation and measurement demonstrates that the proposed antenna system is a good candidate for UWB applications with an operating band extending from 3 to 11GHz, notch-band reconfiguration freedom, and isolation of more than 20dB.

An oscillator is a vital component as the energy source in microwave telecommunication system. Microwave oscillators designed using Gunn diode have poor DC to RF efficiency. IMPact Ionization Avalanche Transit-Time diode (IMPATT) oscillators have the drawback of poor noise performance. The transistorized oscillators have a limitation to the maximum oscillation frequency which means that they cannot be used for oscillators designed for high frequencies. To design negative series feedback Dielectric Resonator Oscillator (DRO), the resonant unit uses a dielectric resonator (DR) since it is small in size, light in weight, has high-Quality ($Q$) factor, better stability and also it is inexpensive. It has the benefits of low-phase noise, low cost, miniaturization, high stability, applicable for devices designed at high frequencies and had already been widely applied, so the research on microwave dielectric oscillator has also been one of the focus of today’s microwave integrated circuits. DRO is widely used in electronic warfare, missile, radar and communication systems. The DRO incorporates High-Electron Mobility Transistor (HEMT) as an active device since it offers higher power-added efficiency combined with excellent low-noise figures and performance. The entire circuit of DRO using HEMT at 26GHz is designed using Agilent Advanced Design System (ADS) software. In this, DRO different measurements of parameters are done such as output power which is typically $+11$dBm for 26GHz DRO, phase noise at 10kHz offset for 26GHz DRO it is 80dBc/Hz. The frequency pushing and frequency pulling for 26GHz DRO its typical values are 30kHz/V and 1MHz, respectively.

Neuromorphic systems are the future computing systems to overcome the von Neumann’s power consumption and latency wall between memory and processing units. The two main components of any neuromorphic computing system are neurons and synapses. Synapses carry the weight of the system to be multiplied by the neuromorphic attributes, which represent the features of the task to be solved. Memristor (memoryresistor) is the most suitable circuit element to act as a synapse. Its ability to store, update and do matrix multiplication in nanoscale die area makes it very useful in neuromorphic synapses. One of the most popular memristor synapse configurations is the two-transistor–one-memristor (2T1M) synapse. This configuration is very useful in neuromorphic synapses for its ability to control reading and updating the weight on a chip by signals. The main problem with this synapse is that the reading operation is destructive, which results in changing the stored weight value. In this paper, a novel refreshment circuit is proposed to restore the correct weight in case of any destructive reading operations. The circuit makes a small interrupt time during operation without disconnecting the memristor, which makes the circuit very practical. The circuit has been simulated by using hardware-calibrated CMOS TSMC 130nm technology on Cadence Virtuoso and linear ion drift memristor Verilog-A model. The proposed circuit achieves the refreshment task accurately for several error types. It is used to refresh 2T1M synapse with any destructive reading signal shape.

In this paper, a real-time low-cost geophone-based Elephant Footstep Vibration Detection and Identification (EFVDI) system is proposed. The system design started with a real-time low-cost generalized Footstep Vibration Recording and Analyzing (FVRA) system. A series of field experiments to record elephant footstep vibration (target) signals and other possible interfering ground vibration (noise) sources are conducted using the FVRA system. System’s actual field performance was evaluated in terms of maximum detection range, signal amplitude, detection ratio, signal frequency, signal time span, etc. Variations of system’s performance with several input parameters are also investigated. The recorded signals from target as well as noise sources are analyzed to extract different Signal Parameters (SPs). All SPs are saved in a Ground Vibration Signal Pattern Library (GVSPL) which is then used to frame accurate indigenous Elephant Identification Algorithm (EIA). The EIA is embedded in FVRA system to reshape it as specific Elephant Footstep Vibration Detection and Identification (EFVDI) system. The EFVDI system has successfully segregated elephant footsteps from other noise vibrations with high accuracy under simulated field experiment. The results from the proposed system will provide important data to the ongoing research of developing the much needed highly accurate Elephant Early Warning System (EEWS) in future.

Most image processing applications are naturally imprecise and can tolerate computational error up to a specific limit. In such applications, savings in power are achieved by pruning the data path units, such as an adder module. Truncation, however, may lead to errors in computing, and therefore, it is always a challenge between the amount of error that can be tolerated in an application and savings achieved in area, power and delay. This paper proposes a segmented approximate adder to reduce the computation complexity in error-resilient image processing applications. The sub-carry generator aids in achieving a faster design while carry speculation method employed improves the accuracy. Synthesis results indicate a reduced die-area up to 36.6%, improvement in delay up to 62.9%, and reduction in power consumption up to 34.1% compared to similar work published previously. Finally, the proposed adder is evaluated by using image smoothing and sharpening techniques. Simulations carried out on these applications prove that the proposed adder obtains better peak signal-to-noise ratio than those available in the literature.

In this work, we have used a novel adaptive neuro-fuzzy inference system (ANFIS) method to design and fabricate a high-performance microstrip diplexer. For developing the proposed ANFIS model, the hybrid learning method consisting of least square estimation and back-propagation (BP) techniques is utilized. To achieve a compact diplexer, a designing process written in MATLAB 7.4 software is introduced based on the proposed ANFIS model. The basic microstrip resonator used in this study is mathematically analyzed. The designed microstrip diplexer operates at 2.2GHz and 5.1GHz for wideband wireless applications. Compared to the previous works, it has the minimum insertion losses and the smallest area of 0.007 ${\lambda }_g^2$ (72.2mm²). It has flat channels with very low group delays (GDs) and wide fractional bandwidths (FBWs). The GDs at its lower and upper channels are only 0.48ns and 0.76ns, respectively. Another advantage of this work is its suppressed harmonics up to 12.9GHz (5th harmonic). To design the proposed diplexer, an LC model of the presented resonator is introduced and analyzed. To verify the simulation results and the presented ANFIS method, we fabricated and measured the proposed diplexer. The results show that both simulations and measurements data are in good agreement, which give reliability to the proposed ANFIS method.

Reconfiguration that alters on/off status of sectionalizing and tie switches attempts to improve the operational performances of distribution networks (DNWs). This paper formulates the reconfiguration problem as a multi-objective optimization problem of reducing the net feeder loss(NFL), improving the node voltage profile (NVP) and enhancing the node voltage stability (NVS) and proposes a new reconfiguration method involving rainfall optimization (RO) for obtaining robust solutions. The method performs search for optimal tie switches in several sets of sectionalizing switches; each set is obtained from a closed loop formed for each tie switch, with a view of reducing the computational burden and adapting a self-adaptive technique for tuning the RO parameters for improving convergence. It performs study on 33-, 69- and 119-node DNWs and exhibits its superior performance over existing methods.

With advancements in computing and communication technologies on mobile devices, the performance requirements of embedded processors have significantly increased, resulting in a corresponding increase in its energy consumption. Dynamic scaling of operating voltage and operating frequency has a strong correlation to energy minimization in CMOS real-time circuits. Simultaneous optimization of ($v$, $f)$ pairs under dynamic activity levels is thus extensively investigated over several years. The supply voltage is tuned dynamically during runtime (DVS), with a fixed threshold voltage, to achieve energy minimization. This work addresses the issue of maximizing the energy efficiency of real-time periodic, aperiodic and mixed task sets, in a uniprocessor system, by developing a novel task feasibility methodology, with a novel processor performance-based constraint, to generate the optimal operating supply voltage to the individual task of task sets. The energy minimization of real-time mixed task sets is formulated as Geometric Programming (GP) problem, by varying frequency for periodic tasks sets and keeping fixed frequency for aperiodic tasks set, over a range of task sets and hence computing optimal operating voltages. Simulation experiments show energy savings on the cumulative basis of 50%, 38% and 29% for periodic, aperiodic and mixed task sets, respectively, based on the processing timing constraints of task sets.

This paper presents an analysis of the Reduced Switching Capacitor Digital-to-Analog Converter (RSC-DAC)-based low power Successive Approximation Register Analog to Digital Converter (SAR-ADC). The proposed structure involves the Low voltage Static D-Latch Comparator (LSD-LC) with pre-amplifier operators in two modes (Normal and Hold), the RSC-DAC switching energy, reduced by 93% contrast to the standard Charge Redistribution Switching Capacitor DAC (CRSC-DAC) method, and the Successive Approximation Register (SAR) control logic. The LSD-LC with pre-amplifier consists of a latch circuit and a pre-amplifier. The pre-amplifier is often used to eliminate the DC offset voltage and kickback noise without substantially weakening the Signal-to-Noise Ratio (SNR) to drive the main circuit while the latch is needed for comparison. The linearity parameters such as Integral Nonlinearity, Differential Nonlinearity and effect of parasitic capacitances of the RSC-DAC are analyzed and improved by the new approach named as Adaptive Random Code Generation (ARCG) Technique. The above overall design is implemented in 250-nm CMOS design of the TANNER-EDA tool, consuming 1.74-mW power at 60MS/s. The proposed structure has an INL and a DNL, respectively, of +0.18/$-0.12$ LSB and +0.11/$-$0.05 LSB.

This paper considers the minimax design of two-dimensional (2D) finite impulse response (FIR) half-band filters. First, the design problem is formulated in a matrix form, where the half-band constraints are expressed as a pair of matrix equations. By matrix transformations, the constrained minimax problem is transformed into an unconstrained one. Then, we propose an efficient iterative reweighted least squares (IRLS) algorithm to solve this problem. The weighted least squares (WLS) subproblems arising from the IRLS algorithm are solved using a generalized conjugate gradient (GCG) algorithm. Moreover, the GCG algorithm is guaranteed to converge in a finite number of iterations. In the proposed algorithm, the design coefficients of filters are solved in their matrix form, leading to a great saving in computations and memory space. Design examples and comparisons with existing methods are provided to demonstrate the effectiveness and efficiency of the proposed algorithm.

This paper proposes a novel method to control leakage and noise in domino circuits for wide fan-in OR logic with low power consumption, low process variation, and higher noise margin under the similar delay condition. In the proposed method, output and dynamic nodes are isolated from the PDN (Pull-Down Network) to improve the noise immunity and reduce switching activity. Further, with the aid of a transistor in the stack, the sub-threshold current is reduced. Thus, the proposed domino is applicable for high-speed and low-power applications in deep sub-micro-range. Simulation results show that the proposed domino improves the noise immunity and figure of merit (FOM) by factors of 1.95 and 2.34, respectively, with respect to the conventional domino with a footer. Along with this improvement, 26% reduction is also observed in power consumption. The entire simulations for all the domino circuits are done at 45-nm CMOS technology by using SPECTRE simulator under the Cadence Virtuoso environment.

A low voltage low power two-stage CMOS amplifier with high open-loop gain, high gain bandwidth product (GBW) and enhanced slew rate is presented in this work. The proposed circuit makes use of folded cascode g_m-boosting cells in conjunction with a low voltage gain enhanced cascode mirror using quasi-floating gate (QFGMOS) transistors. QFGMOS transistors are also used in input pair and adaptive biasing, which facilitate large dynamic output current in the presented circuit. Consequently, the slew rate is enhanced without much increase in static power dissipation. The unity gain frequency (UGF) and dc gain of the circuit are 29.4MHz and 132dB, respectively. The amplifier is operated at 0.6V dual supply with 89$\mu$W power consumption and has a nearly symmetrical average slew rate of 51.5V/$\mu$s. All simulations including Monte Carlo and corner analysis are carried out using 180-nm CMOS technology for validating the design with help of spice tools.

A compact wearable textile antenna with multiband and circular polarization characteristics is proposed in this work for Wireless Body Area Networks (WBAN). An asymmetrically connected vertical stub as a radiator with the partial ground for quad-band (3.03–3.76GHz, 5.48–6.24GHz, 7.10–7.40GHz, 7.93–8.22GHz) operation and horizontal stubs on the radiator with L-slots in the ground is proposed for the triple band (3.16–3.22GHz, 7.25–7.36GHz and 7.93–8.08GHz) circularly polarized radiation. Jeans fabric is used as substrate with dielectric constant $(\epsilon r)=1.7$ and loss tangent ($\text{tan}\delta =0.025$). The dimensions of the proposed antenna are $50\times 30\times 1$mm³. Various conductive fabrics are investigated and analyzed as a radiating element. The proposed jeans antenna provides the gain ($>5$ dB) and radiation efficiency ($>90$%) for all operating bands. The impact of the human body right arm loading on the antenna has been presented in terms of the reflection coefficient ($S_{11}$) and gain using the CST Microwave studio simulation environment. The proposed antenna provides stable performance under bending conditions and the SAR values that are under acceptable limits ($<2$W/kg for 10g of tissue). The flexibility, compactness and radiation properties make it suitable as a wearable textile antenna for off-body communication applications.

Existing block-level defect detection method in patterned fabric causes a large number of false detections due to the lack of edge information. To solve this problem, in this paper, we propose a bilayer Markov random field (BMRF) method for inspecting defects in patterned fabric. First, the proposed method reduces samples of the original fabric image to obtain the constraint layer, which can locate the defective block roughly. Second, we interpolate samples into the image to supplement the local information to improve and optimize the imperfect boundary, to obtain a more detailed data layer. Moreover, this paper proposes a new potential function, which considers the differential characteristics of the image blocks in the same layer and the transition probability between different layers. Finally, this paper utilizes a parameter estimation method based on the expectation maximization to solve the parameters of the BMRF method. The proposed BMRF method is evaluated on databases of star-, box- and dot-patterned fabrics. By comparing the resultant and ground-truth images, the recall rate of the proposed method in the three patterned fabrics is 95.32%, 89.29% and 93.28%, respectively, which is comparable to the existing methods.