Journal of Circuits, Systems and Computers

The design of reversible logic circuits has received considerable attention in recent times for their potential use in implementing quantum computers. A fault model, namely, the Missing-Gate Fault (MGF) model, has been found to be more suitable for modeling defects in quantum circuits as compared to the classical fault models used for testing conventional CMOS circuits. In this paper, we propose two design-for-testability techniques with universal test set to detect MGFs in a reversible circuit. In these techniques, an $(n\times n)$ reversible circuit implemented with $k$-CNOT gates is transformed to a testable design with addition of two extra inputs lines and some additional gates, which uses a universal test set of size $(n+2)$ to detect the MGFs. The proposed DFT techniques are compared with earlier works and it has been shown that these techniques outperform the earlier techniques with respect to quantum cost overhead and percentage detection of the different MGFs.

Rolling bearings are pivotal components in industrial rotating equipment and the issue of fault will occur inevitably due to long-term abrasion. This study proposes a novel GA-BP neural network (GA-BPNN) algorithm to improve the accuracy of fault diagnosis of industrial rolling bearings. The genetic algorithm (GA) is employed to optimize the structure, initial weight and threshold of BP neural network, which can improve the ability of diagnosis and reduce the time of network training. At first, the structure of network is determined so that the optimal parameters of GA can be given, then the population of GA will be encoded. At second, the individual fitness function is calculated based on the test error norm of the BP neural network, as a criterion for distinguishing the individual from individual. The optimal weight and threshold are obtained by means of the corresponding selection, cross and variation, etc. Finally, the simulation experiment is carried out in Matlab and massive vibration experimental data of industrial rolling bearing are utilized. To verify the ability of the proposed novel GA-BPNN, compared with BP neural network algorithm (BPNN), the convergence speed and accuracy of GA-BPNN are better. The results of experiment illustrate that the optimized GA-BPNN method can identify the fault-type quicker, and has higher feasibility, which can be used to assist diagnosis of industrial bearing and improve efficiency.

Shunt active filters (SAFs) can be used for harmonic mitigation, reactive power compensation and power factor control in electrical distribution networks. Model predictive controller (MPC) can be used to give optimum performance for SAF’s due to its inherent cost function optimization. The SAF’s reference current extraction technique in finite control set-MPC (FCS-MPC) plays a vital role in the effectiveness of the SAF’s operation. The advantage of FCS-MPC is that it closely tracks the reference and injects the required compensating currents by optimizing the SAF’s switching vector and it does not require an external modulator for pulse generation. FCS-MPC can be implemented as either an optimal switching vector MPC (OSV-MPC) or an optimal switching sequence MPC (OSS-MPC) technique. The OSV-MPC technique is simple and efficient for SAF applications. In this paper, a novel reference current extraction technique, the inverse matrix average pq-synchronous reference frame (SRF) (IMApq-SRF) technique, is proposed along with the OSV-MPC technique. Practically a two-step delay compensation is essential in the implementation of the technique for the control of an SAF. Hence in this paper a two-step horizon OSV-MPC technique is proposed along with an IMApq-SRF reference current extraction technique to improve the power quality in distribution networks. The presented results show that the proposed methodology gives optimum SAF performance under a large range of supply and load conditions.

The realization of capacitance multiplier using the versatile active building block, namely voltage differencing differential difference amplifier (VDDDA) is presented in this paper. The realized capacitance multiplier is very simple consisting of one VDDDA, one MOS resistor ($R_M)$ and one grounded capacitor which is attractive for integration. The multiplication factor (KC) of the realized circuit can be electronically controlled via the bias current ($I_B)$ and control voltage ($V_C)$ without the need of any matching condition of active and passive element. Moreover, the multiplication factor can be adjusted to be more or less than one. The performances of the presented capacitance multiplier are verified through Pspice simulation using CMOS VDDDA in 0.18$\mu$m TSMC technology with $\pm 0.9$V power supplies. The multiplication factor is designed to be $K_C=2$ by choosing $V_C=0.85$V, $I_B=50$$\mu$A and $C=30$ pF. The simulated multiplication factor is around 1.98. The simulated operational frequency range is around three decades (6.16 kHz–8.91MHz). The performances of the proposed circuit are also verified by the experiment using VDDDA implemented from the commercial ICs, AD830 and LM13700 with $\pm 5$V power supplies. The experiment is conducted under the same multiplication factor ($K_C=2$) as the simulation by choosing $R_M=0.27$ k$\mathrm{\Omega }$ (1% passive resistor), $I_B=96.2$$\mu$A and $C=1$nF. The experimental multiplication factor is around 2.06. The experimental operational frequency range is around three decades (1kHz–1.25MHz). By adjusting the bias current from 17.67$\mu$A to 400 $\mu$A, the experimental multiplication factor is controllable from 11.47 to 0.48. The percent deviation of the theoretical and experimental multiplication factor is lower than 5% when the value of bias current is greater than 39$\mu$A. These deviations stem from the effect of the parasitic capacitance and resistance in VDDDA. Moreover, the application example of the presented capacitance multiplier as the sinusoidal oscillator is presented. The performances of the presented oscillator verified via the experiment are well consistent with theoretical anticipation.

This paper presents a novel sub-1-V CMOS voltage reference with high power supply rejection ratio (PSRR), low line sensitivity, and low supply voltage. CMOS voltage references available in the literature use a self-biased cascode branch consisting of two MOS transistors operating in the subthreshold region to generate the proportional-to-absolute-temperature (PTAT) voltage only, whereas extra circuitry is required to generate the complementary-to-absolute-temperature (CTAT) voltage for temperature compensation. But in the proposed sub-1-V CMOS voltage reference, both the PTAT and CTAT voltages are generated using a single self-biased cascode branch. Two operational amplifiers in negative feedback topology are used to convert the PTAT and CTAT voltages into PTAT and CTAT currents, respectively, which help to enhance the stability and PSRR of the proposed voltage reference. The proposed voltage reference has been designed and simulated in 180-nm standard CMOS technology using Cadence Virtuoso Analog Design Environment. The proposed voltage reference achieves an output reference voltage of 424.85mV with a temperature coefficient of 29.5ppm/^∘C for the temperatures ranging from $-55^{\circ }$C to 125^∘C at a supply voltage of 0.8V. A line sensitivity of 0.0035%/V is achieved for the supply voltage varying from 0.8V to 5V at nominal temperature (27^∘C). A PSRR of $-$91.69dB is observed for the frequencies ranging from 1Hz to 10kHz at nominal conditions without using any capacitive filter. Also, the output noises of the proposed design at nominal conditions for the frequencies of 1Hz and 10kHz are obtained as 2.37$\mu$V/$\surd$Hz and 45.26nV/$\surd$Hz, respectively.

This paper presents an improved multi-objective mayfly algorithm (IMOMA) to resolve the optimal power flow (OPF) problem in a regulated power system network with different loading conditions. The OPF problem, considered a multi-objective optimization problem, comprises multiple objective functions related to economic, technical, operational and security aspects. The IMOMA algorithm has been developed by implementing the simulated binary crossover (SBX), polynomial mutation and dynamic crowding distance (DCD) operators in the original multi-objective mayfly algorithm (MOMA).The OPF problem is analyzed by considering multiple objective functions in the IEEE30-bus test system, the IEEE118-bus test system and the 62-bus Indian utility system. The hypervolume performance metric is used to compare the performance of the MOMA and IMOMA with respect to different operating scenarios. Further, loading conditions ranging between 150% and 50% of the base load are considered for the evaluation. The effectiveness of the IMOMA over the MOMA is observed from the results of the different loads. The best compromise solution is obtained from a set of pareto optimal solutions by implementing the TOPSIS method.

As the semiconductor industry strives for downsizing and high speed, it is confronted with increasing scaling uncertainty as devices decrease to the nanoscale. Nano-magnetic logic (NML) is an alternative approach to synthesize the digital logic circuits with high-density and low-power consumption. We introduced an optimal design of content addressable memory (CAM) memory based on perpendicular nano-magnetic logic (pNML). The main aim of this implementation is to synthesize CAM memory in terms of latency and other design parameters. The implementation of the design is a multilayer approach, which is optimal. The synthesis approach and optimization are perfectly scalable across layout construction of designs. Here a new logic gate in pNML technology is designed which is mainly used for matching of two input numbers. According to insight, both memory unit and a matching unit in the pNML are introduced in the state-of-the-artwork for the first time to synthesize design in high-speed pNML application. MAGCAD tool is used for the design of all the proposed pNML layouts.

A new architecture of 4-bit reversible multiplier with scalability factor of order $4N$ is presented in this paper. The design procedure is based on a unique method of gates placement, which produces parity preserving circuits. This property facilitates graceful testing and full coverage of single-bit faults at lower overhead. The circuit is designed and implemented on the top of reversible analyser for obtaining operating costs in terms of number of wires, gate cost, quantum cost, garbage output and ancilla input. Testable implementation of recently reported multiplier circuits has also been performed using the existing method of testing under the same platform. This work achieved a reduction of up to 33% in operating costs when all the parameters are combined together.

With the rapid development and application of autonomous technology in vehicles, we are going to see more autonomous vehicles on the roads in a foreseeable future. While autonomous vehicles may have the advantage of reducing traffic accidents caused by human drivers’ neglect and/or fatigue, one of the challenges is how to develop autonomous driving algorithms such that autonomous vehicles can be safely deployed in a mixed traffic environment with both autonomous vehicles and human-driven vehicles. Instantaneous lane-changing type may be significantly different for human drivers, which would lead to traffic accidents with other vehicles including autonomous vehicles. In this paper, we propose a resilient algorithm for the prediction of the human driver’s lane-changing behaviors. The proposed algorithm uses a long-short term memory (LSTM) classifier to identify the conservative lane change and the aggressive lane changing and accordingly makes the accurate prediction on lane changes in the driving of vehicles by human drivers. The proposed method provides a useful addition in facilitating the design of more advanced driving algorithms for autonomous vehicles. Using the vehicle trajectory data in the NGSIM data set for a large number of simulations, the effectiveness of this method has been confirmed.

Inverse algorithms are used to assess EEG source parameters. This involves identifying unknown voxels in hundreds of different regions, giving an incomplete picture of the brain. There are no uniform solutions since the same sensor output may come from many source configurations. To overcome the lack of uniqueness, one must consider previous information and parameters inherent in the source. Our goal is to predict the location of brain sources from the recorded EEG signal without any prior knowledge of sources. We applied a particle filter to locate the brain sources in this article. The degeneracy of particle weights limits the particle filter’s performance. Various resampling techniques are suggested to address this problem. The performance of the branching resampling approach is compared to a systematic resampling method for brain source localization. To perform assessment and comparison studies, both simulated and real EEG data are used.

In this paper, a new structure using dual junctions in the source and drain regions is proposed to improve the electronic characteristics of the doping less carbon nanotube FET. To simulate the proposed structure, the Poisson–Schrodinger equation self-consistent solution method through the nonequilibrium Green’s function (NEGF) procedure has been used. The proposed structure is formed by dividing the source and drain regions into two parts with the same lengths and different work function for each part. The simulation results show that the short channel effects (SCEs) including the sub-threshold swing (SS) and the drain-induced barrier lowering (DIBL) are improved. Also, OFF current has a significant reduction, which in turn increases the current ratio. Besides, improving the ambipolar behavior and leakage current are other benefits of the proposed structure.

As a third generation artificial neural network, spiking neuron network is expected to expand the artificial intelligence world. However, as a more detailed simulation of brain, a single run of spiking neural networks (SNNs) simulation can take hours to days. To get a better prediction of SNN simulation performance, existing work requires gathering result of actual runs to conduct accurate modeling. In this paper, we propose a nonempirical SNN simulation performance prediction method, prototyped in a hybrid CPU-FPGA cluster. Experiments show that our method, without actual simulation run, can get comparable accuracy with orders of magnitude less runtime cost.

In this paper, two new first-order voltage-mode all-pass filters (APFs) are proposed. Each of the proposed APFs comprises a single modified DDCC-, and has high input impedance. The first and second APFs can provide first-order noninverting and inverting APF responses, respectively. As passive elements, the first APF comprises two grounded capacitors, and a floating resistor while the second one uses a grounded resistor, a floating resistor and a grounded capacitor. However, both of the APFs suffer from a matching problem. Two quadrature oscillators (QOs) obtained from the APFs are presented. Simulations of the APF and QO circuits are fulfilled via the SPICE program. Besides, diverse experiments for the APFs are made to verify the performances.

In this work, we have presented the design of voltage level shifter using carbon nanotube field effect transistors (CNTFETs). The proposed design is capable of converting two input voltage levels to two output voltage levels. The threshold voltage of CNTFETs is suitably chosen to achieve the desired output. The proposed design can perform both up and down shifting which is very useful in the system-on-a-chip design to interface with other peripherals. It exhibits lower delay and power delay product in comparison with the existing complementary metal–oxide–semiconductor-based voltage level shifters. The proposed circuit is very effective as it eliminates the requirement of additional voltage level shifter for designing systems with multi-power supply voltage domain in the nanoscale regime. The design has been analyzed for different process, voltage and temperature corners. It has been shown that the design works perfectly with $\pm 10\%$ variation in the diameter of the carbon nanotubes used in the CNTFET. The performance varies slightly with $\pm 10\%$ variation in operating voltage. Our analysis shows that the design is thermally stable for a wide variation in operating temperature.

In switching algebra, there exist standard forms of Boolean functions such as the disjunctive or conjunctive form. This paper discusses the theory of the extended standard forms of Boolean functions. In addition to the four existing standard forms, two further forms are introduced and thus expanded to six basic forms. On the one hand, the existence of the extended forms is presented and on the other hand new formulas and equations are illustrated. Equations relating to the resolution and/or solution of conjunction/disjunctions are detailed and proven to be valid. In addition, equations for conversion between forms are exemplified. Finally, certain formal relations between the basic forms that are valid under certain conditions are featured.

The high-dimensional convolution, in either linear or nonlinear form, has been employed in a wide range of computer vision solutions due to its beneficial smoothing property. However, its full-kernel implementation is extremely slow. We do need a fast algorithm for this important operation. To solve this problem, we propose an acceleration pipeline assembled by three steps: $d$-D nonlinear convolution $\stackrel{1}{\Rightarrow }$ $d$-D linear convolution $\stackrel{2}{\Rightarrow }$ 1-D dimensional convolution $\stackrel{3}{\Rightarrow }$ 1-D recursive box filter. Thanks to the low computational complexity of box filtering, we speed up the computation significantly. Roughly speaking, our contribution is two-fold: (1) establishing the connection between the high-dimensional convolution acceleration algorithm and tensor decomposition; (2) propose total four acceleration technologies including demultiplexing–blurring–multiplexing framework, convolution decomposition, periodic tensorization and recursively box filtering to compose our acceleration pipeline under the line of the above connection. The effectiveness of these techniques is demonstrated in various comparisons and experiments. The running times of various applications are largely shortened from several minutes to fewer seconds or less.

This paper presents a design and simulation of a low-noise, low-voltage, and low-power complementary metal oxide semiconductor (CMOS) logarithmic amplifier for biomedical applications like digital hearing aid applications. The amplifier block of analog front end is used as a logarithmic amplifier, based on the progressive-compression parallel-summation architecture with DC offset cancelation by adding an off-chip coupling capacitor at each stage. A fully nontailed differential limiting amplifier with bulk-driven input pair is used to achieve larger voltage gain and low voltage operation. The proposed logarithmic amplifier was designed and simulated with process parameters variation in standard 0.18-$\mu$m CMOS technology. The circuit operates with a single 0.4-V power supply voltage and dissipates 0.832$\mu$W. The simulated input dynamic range is about 60dB, which covers the input amplitudes ranging from 1$\mu$V to 10mV, and the $-$3-dB bandwidth of the amplifier is from 400Hz to 8.27kHz with simulated total input-referred noise is 0.731$\mu$V@8 kHz.

This paper presents the implementation of two digital noise-cancellation circuits (DNCCs) using a proposed algorithm and a Karnaugh map for a $2+1$ multistage noise-shaping (MASH) delta-sigma modulator (DSM). The MASH architecture inherits a superior signal-to-noise-and-distortion ratio (SNDR) with the aid of an efficient noise-cancellation technique either in the analogue or digital domain. The key motivation of this study was to design an area-efficient DNCC. The first approach employed a proposed algorithm (Algorithm-based DNCC) to implement the DNCC and to construct a delay block with an inverter and transmission gate. The second approach involved a Karnaugh map (K-map DNCC) and a delay block with a pair of D flip-flops. A maximum simulated signal-to-noise ratio of 135dB was completed with optimal analogue scaling coefficients for the proposed $2+1$ MASH DSM with DNCC. The simulated SNDRs of the Algorithm-based DNCC and K-map DNCC were 91.04dB and 91.16dB, respectively. Measured results show that the SNDR of the Algorithm-based DNCC, the SNDR of the K-map DNCC, power consumption and core area are approximately 58.7dB, 62.1dB, 0.26$\mu$W and 2275$\mu$m², respectively, for the designed DNCCs with an operating frequency of 10.24MHz and supply voltage of 1.8V. The transistor counts of the Algorithm-based DNCC are 74 transistors, while they are 106 transistors for the K-map DNCC. The proposed Algorithm-based DNCC saves 32 transistors and approximately reduces its chip area to 69.8% of the K-map DNCC.