Journal of Circuits, Systems and Computers

Artificial Intelligence (AI) is a new technical science that studies and develops theories, methods, techniques and application systems for simulating, extending and expanding human intelligence. This paper is based on the research of AI in the auxiliary guidance function of athletes’ standard training in physical education. It aims to conduct data mining from different aspects such as different joint angular speeds, motion injury screening and different parts of sports injuries and then integrate these aspects. Create a way to reduce athletes’ injuries and scientific training. In order to improve the recognition efficiency of athletes’ movement patterns, nonlinear auto regressive neural networks are used to recognize the movement patterns of athletes’ limb surface signals. Through this research work, it can provide a certain reference basis and practice platform for the research on the auxiliary guidance role of AI in the sports standard training of athletes in physical education. Performance design and implementation include four modules: Image acquisition, preprocessing, motion detection and human motion recognition. Between them, the image acquisition module uses a memory mapping path to determine the format of the camera frame image, and the image format conversion is completed through channel conversion. Experimental data shows that athletes’ strength quality, speed of action response, technical continuity, psychological stability and physical control ability have all been greatly improved. Among them, the most obvious is that with the assistance of AI technology, the psychological stability has reached 9.2; the strength quality has reached 9.1.

Software Defect Prediction (SDP) involves the early detection of fault-prone modules and reduces the testing efforts and cost. Support Vector Machine (SVM)-based SDP classifiers use large amount of high-dimensional data, and hence feature selection (FS) is applied for better accuracy. Search-based feature selection is found effective to improve the efficiency of predictors. This paper proposes a genetic evolution (GeEv) technique to select features. The GeEv technique involves introduction of diversity at intermediate level by the genetic evolution of random offspring with better survival capability. GeEv searches the feature space for an optimal feature subset using the performance of classification and number of features selected as the fitness function. The FS is modeled as an optimization problem and optimal solution is sought using GeEv. The performance is compared with baseline technique. From the experimental results, it is shown GeEv outperforms the competing FS approach and can achieve better accuracy than others statistically.

In order to succeed in our everyday life, efficient performance of the power system is of utmost importance, and hence, all the sub-sectors of the power system should be analyzed for the purpose of achieving efficiency and accuracy. It must also be remembered that load forecasting assists a lot to improve the power system. Moreover, it contributes substantially to formulate logical approaches for emerging short-term load forecasting (STLF) for all days including the distinct days and make them follow a uniform standard. Of all the techniques which have been applied so far, honey bee-optimized Euclidean norm, based on fuzzy inference system, is used for identifying the problems, and in addition, support vector classifier is utilized to prepare the STLF models. Parameters — temperature, humidity, monsoons, wind, cloud density, dew point, season, hour of the day, day of the week, distinct day, and holiday — have been taken into account for the current study. A well-prepared database can be used for regression which will be of immense help to forecast the load using artificial intelligence. For every day of a month, the MAPE is computed (using the forecasted and actual hourly values) in order to observe the accuracy of STLF. The planned method has been very successful for the load forecast of all days for all seasons. The forecast has been done using the technique for a real time data of one year (test forecast year) with a historical dataset collected for a period of two years, and the results obtained for all seasons have been found to be satisfactory. STLF has helped to find better values due to its pace, and become healthier than other methods already in practice. With the advent of smart grid, the data will be accessible at more granular level as smart meters have capability to provide consumer load, usage data on-line and this facility will be of great help to utility operators and planners for operations on-line. How to use the data available from smart meters for better STLF is a challenging task and it would draw much attention for future research.

In this paper, we propose a low-jitter reference-less clock and data recovery (CDR) circuit with a speed range of 9.8–12.5Gb/s. The proposed CDR uses a multi-stage half-rate bang-bang phase detector (ML-HR-BBPD) to maximize the quantization of the phase difference. In addition, a unit interval adjuster (UIA) is added to the CDR circuit. So that the circuit can minimize the phase detector’s phase error before the output clock frequency is locked. Finally, the loop filter (LF) is improved to realize the coarse and fine adjustment of the phase error over a wide range of phase differences. The CDR circuit’s total power consumption is reduced by using a half-rate phase detector. The CDR circuit was fabricated in TSMC 40nm CMOS process. The measured results are obtained in the proposed CDR circuit at a data rate of 12.5Gb/s. With a pseudo-random bit sequence (PRBS) of $2^{31}-1$, the measured result shows that the bit error rate (BER) is $<{10}^{-12}$, and the root mean square jitter recovered in the output is 0.302 ${ps}_{\mathrm{\text{rms}}}$. The circuit’s jitter tolerance (JTOL) is 0.46 UI_pp, and its total power consumption is 74.8mW with a 5.98pJ/bit energy efficiency.

This paper proposes the idea of mathematical modeling of the buck converter. The modified approach is achieved through the relay feedback (RF) method and the changes are introduced on the converter output with a soft start. Mathematical modeling of the buck converter is achieved by the state-space model (SSM) and converter’s transfer function (TF) to attain stability. By iteration, the proportional-integral (PI) parameters are tuned by a controller that is incorporated in the RF. The output voltage changes are introduced by maintaining the relay-tuned PI control. The concept requires small tuning times which is obtained at a reduced cost. The effectiveness of buck converter using RF is validated in simulation and hardware.

In this paper, we propose a tree-like branching network for image super-resolution. Specifically, the network consists of information divide-and-conquer groups (IDCG) to preserve the low-frequency structure of images as well as restore high-frequency information. The kernel of IDCG contains several essential components: (a) a simple attention module and an effective residual attention module to maintain low-frequency structures and restore high-frequency information, (b) a novel local merge cell alleviates information redundancy that flexibly and adaptively fuses multiple informative features from different states. Lastly, a multi-scale aggregation unit is designed to improve the final reconstruction. Through a series of experiments, we prove that our method is more effective than previous state-of-the-art results in both quantitative and qualitative evaluation.

Direct digital frequency synthesizer (DDFS) have been proposed extensively as the main structure block in modern wireless communication systems for the complex demodulation process. One of the major design constraints of the performance of DDFS is power dissipation. In this work, efficient implementation of the phase to Sine/Cosine mapping of DDFS is proposed to accomplish less amount hardware and low power dissipation based on the logarithm scheme. The logarithm arithmetic is exploited in the implementations of the sinusoidal functions to simplify the generation process to attain a low-power and low-cost DDFS. The generated Sine/Cosine function is approximated based on the Taylor polynomial approximations. The proposed architecture utilizes efficient logarithm converter units to implement the phase to Sine/Cosine mapping instead of using costly multipliers and squarers. The proposed logarithm-based DDFS scheme demonstrates a reduction in power dissipation with respect to previously proposed work. The proposed architecture produces a spurious-free dynamic range (SFDR) of up to 117 dBc.

In this paper, we introduce a unified nonlinear injection locking model of a large class of 1:2 frequency dividers. The model is valid for two-stage dividers, injected with two-phase or single-phase current or voltage sources. We show that this class of dividers can be rigorously analyzed using the theory of planar nonlinear dynamical systems. We provide accurate compact expressions for the locking range, amplitude, frequency and phase noise. The formulas are validated for two types of frequency dividers using simulations.

Extensive large-scale data and applications have increasing requests for high-performance computations which is fulfilled by Chip Multiprocessors (CMP) and System-on-Chips (SoCs). Network-on-Chips (NoCs) emerged as the reliable on-chip communication framework for CMPs and SoCs. NoC architectures are evaluated based on design parameters such as latency, area, and power. Cycle-accurate simulators are used to perform the design space exploration of NoC architectures. Cycle-accurate simulators become slow for interactive usage as the NoC topology size increases. To overcome these limitations, we employ a Machine Learning (ML) approach to predict the NoC simulation results within a short span of time. LBF-NoC: Learning-based framework is proposed to predict performance, power and area for Direct and Indirect NoC architectures. This provides chip designers with an efficient way to analyze various NoC features. LBF-NoC is modeled using distinct ML regression algorithms to predict overall performance of NoCs considering different synthetic traffic patterns. The performance metrics of five different (Mesh, Torus, Cmesh, Fat-Tree and Flattened Butterfly) NoC architectures can be analyzed using the proposed LBF-NoC framework. BookSim simulator is employed to validate the results. Various architecture sizes from $2\times 2$ to $45\times 45$ are used in the experiments considering various virtual channels, traffic patterns, and injection rates. The prediction error of LBF-NoC is 6% to 8%, and the overall speedup is $5000\times$ to $5500\times$ with respect to BookSim simulator.

With China’s economic transformation into a high-quality development stage, the importance of credit system construction has become increasingly prominent. The problems existing in the current telecom credit system include: (1) insufficient coverage of credit features; (2) traditional credit assessment models are difficult to reflect user credit status objectively, comprehensively and timely; (3) user demand for credit management and credit services are ignored. Due to these deficiencies, a new multi-level credit system is necessary to meet the rapid development of market economy. Telecom operators have large amount of precious data, with the advantages of large-scale, high-precision and data-diversity, which can provide new ideas for the construction of credit system. This work focuses on the current problems and conducts research as follows: design a Telecom Credit Assessment Model based on Boosting and Stacking ensemble techniques, called TCAMBS, to improve the evaluation accuracy, and to select the best model according to the experimental results. On the one hand, this work can promote the innovation of telecom credit assessment models and provide new ideas for the construction of the credit system. On the other hand, this work will also help telecom operations to improve the quality of telecom credit services.

Wireless Multimedia Sensor Networks (WMSNs) are mostly affected by bottleneck issues, high packet loss, increased delay, and minimum throughput. One of the most effective schemes towards controlling the bottleneck on the web is traffic control. The WMSNs handle different types of data, hence QoS is essential to afford trustworthy as well as reasonable services towards these kinds of data. The existing congestion control methods, FTLP and FEWPBRC consider the frequency of packet transmission and decide on the output transmission rate of the sink. In the Fuzzy-Based QoS Alert Bottleneck Mechanism, the probability of congestion is predicted by using a fuzzy inference system with three special congestion indicators, and the traffic rate is adjusted based on the priority of the real-time and non-real-time applications. The FBQACC is simulated using the NS2 simulator and it gives an improvement in the average throughput FTLP and FEWPBRC by 7.1499% and 6.3327%, respectively. Similarly, FBQACC reduces average delay compared to FTLP and FEWPBRC by 11.074% and 7.8128%, respectively. The proposed work also gives a minimized average packet loss percentage compared to the existing congestion control methods.

A power factor correction (PFC) scheme for the Inverse Watkins Johnson Converter (IWJC) drawing power from a single-phase AC source, delivering polarity reversible DC voltage output is presented in this paper. The IWJC is basically a DC-to-DC converter which can deliver a boosted positive output voltage or a negative output voltage with buck or boost feature. It is suitable for driving DC loads, typically, DC motors in forward or reverse direction. Unlike the conventional four quadrant DC chopper, the IWJC can boost the input voltage and deliver a voltage higher than the source voltage with duty cycle controlled polarity reversible feature. This paper presents the methodology of including a PFC strategy for the IWJC, when fed from a single-phase AC supply. The proposed methodology has established that the AC source side power factor is unity and that the source current is maintained sinusoidal. Simulations and experimental verifications validate the proposed idea.

Adders are one of the essential blocks of Arithmetic Logic Unit (ALU), addressing the memory, table indices and many more such types of applications. The speed of the adder unit more often decides the performance of CPU (Central Processing Unit) and GPU (Graphics Processing Unit) for graphics applications. The high-speed design is a very important performance parameter speed that too with less implementation area and low power consumption. In this paper, the author proposes a novel 32-bit Residue Hybrid Adder (RHA) using the Residue Number System (RNS) and implemented using a Hybrid CMOS/PTL logic style. An RNS has the advantage of representing a large integer using a set of few smaller integers to make computation more efficient and effective. On the other side, parallel prefix adders provide faster execution time as it performs the operation in parallel. With our paper, it is evident that RHA gives better performance in terms of delay, power consumption and area for arithmetic operations. The experimental analysis has been performed using the EDA tool on 45-nm CMOS technology. The power, delay and power delay product (PDP) performance parameters are compared with the existing adders and the results show that, thanks to smaller modules, proposed units have both smaller area and delay by up to 45% and 41%, and, consequently, they allow achieving up to over 46% power saving, respectively.

The need for identity authentication has become essential in various aspects of people’s life. In this paper, we propose a novel biometric authentication strategy based on music-induced autobiographical memory electroencephalogram (EEG). Specific music is used to induce the stable autobiographical memory, while the EEG signals are collected through the memory process. Users can authenticate themselves by recollecting their minds when listening to the music, which is closely related to their long-term memory. Based on six types of EEG features from 12 subjects, mean F1 score of 0.937, 0.936 and 0.968 are achieved using Logistic Regression, Support Vector Machine and RUSBoost classifier, respectively. This promising result indicates the high distinctive characteristics in music-induced autobiographical memory EEG, which is suitable for identity authentication applications.

This paper presents a $2\times \mathrm{\text{VDD}}$ tolerant I/O buffer with low voltage (VDD) devices. A novel bootstrap circuit for mixed voltage I/O buffer is proposed to solve the unwanted leakage paths and gate oxide reliability issues. The proposed circuit is designed using 1.8V thick gate devices in 22-nm FinFET technology with 1.8V signaling and tolerant to 3.3V. The structure can be used in any CMOS technology for $2\times \mathrm{\text{VDD}}$ tolerant I/O buffer.

This paper presents a new design for the optimization of analog to digital sigma delta-coupling noise annotations. The proposed technique increases the level of the signal-to quantization-noise-ratio (SQNR) by improving the zero of the noise transfer function, which leads to an increase in signal to noise. In the new SQNR design, the modulator rises up to 8.5 db. The proposed structure of the first-order dual-channel sigma-delta modulator is also presented.

In this paper, a highly efficient tree-shaped fractal antenna with multi-broadband resonance characteristics is proposed. The proposed antenna exhibits broad operating bandwidth, high gain, and high efficiency characteristics due to the suggested modifications in the antenna geometry. The suggested circular patch is modified by introducing slots in the form of a tree-shaped fractal structure, and the partial ground plane is modified by incorporating a narrow rectangular slot. The proposed antenna is designed on an FR4 substrate of $40\times 25.05\times 1.6$mm³. The prototype of the proposed antenna has been fabricated and tested to justify the simulation results. The measurement results are in good agreement with the simulation that validates the multi-broadband design approach of the proposed fractal antenna. As per the measurement results, the proposed antenna operates at four distinct bands with $-$10dB impedance bandwidths of 600MHz (2.2–2.8) GHz, 1070MHz (3.3–4.37) GHz, 2550MHz (4.75–7.3) GHz, and 2200MHz (9.7–11.9) GHz. Furthermore, a high peak gain of 10.23dB and a peak radiation efficiency of 96.65% are recorded for the suggested fractal antenna. The suggested compact bandwidth enhanced multi-band antenna can be useful for several wireless communication systems such as wireless fidelity (Wi-Fi), wireless local area network (WLAN), Bluetooth, long-term evolution (LTE), C, S and X bands.

Transient modeling analysis of the traditional DC/DC converters shows their worse effect of nonminimum-phase characteristics due to right-half-plane (RHP) zero existence in their plant transfer function. This RHP zero restricts the bandwidth of the switching converters and, that is the main reason for slower response. The motivation of this paper is to present a new technique for eliminating the RHP zero from the dynamics of a conventional boost converter that can solve the problems associated with the nonminimum phase converters and, to focus on its analysis, design and modeling to achieve a high voltage gain as well as the RHP zero cancellation. The proposed technique uses a transformer combined with switching capacitor cells. The striking feature of the suggested topology is its minimum-phase structure, further enhancement of the voltage gain, switching stress reduction, achievement of an improved frequency response and easiness for the design of a closed-loop control scheme to perform the voltage trajectory tracking task. First, the operation of the proposed converter is identified and then, the corresponding circuit performance is evaluated. By using a suitable design, the control-to-output-voltage transfer function is completely free from the RHP zero. The significant advantages of the proposed converter are established via comparisons. To confirm the design approach and theoretical findings, the simulations are introduced and, numerical experimental results such as Bode diagrams are presented.