Journal of Circuits, Systems and Computers

In this paper, the effects of successively applied static/pulsed negative bias temperature (NBT) stress and irradiation on commercial p-channel power vertical double-diffused metal-oxide semiconductor (VDMOS) transistors are investigated. To further illustrate the impacts of these stresses on the power devices, the relative contributions of gate oxide charge ($N_{\mathrm{\text{ot}}}$) and interface traps ($N_{\mathrm{\text{it}}}$) to threshold voltage shifts are shown and studied. It was shown that when irradiation without gate voltage is used, the duration of the pre-irradiation static NBT stress has a slightly larger effect on the radiation response of power VDMOS transistors. Regarding the fact that the investigated components are more likely to function in the dynamic mode than the static mode in practice, additional analysis was focused on the results obtained during the pulsed NBT stress after irradiation. For the components subjected to the pulsed NBT stress after the irradiation, the effects of $N_{\mathrm{\text{ot}}}$ neutralization and $N_{\mathrm{\text{it}}}$ passivation (usually related to annealing) are more enhanced than the components subjected to the static NBT stress, because only a high temperature is applied during the pulse-off state. It was observed that in devices previously irradiated with gate voltage applied, the decrease of threshold voltage shift is significantly greater during the pulsed NBT stress than during the static NBT stress.

As the feature sizes of integrated circuits are reduced to the nanometer scale, the total soft error rate (SER) in memory and the proportion of multiple bit upsets (MBUs) are significantly increasing. In order to ensure the information reliability, many error correction codes with strong error correction ability were proposed, such as Reed–Somolon (RS) code and Bose–Chaudhuri–Hocquenghem (BCH) code. However, these error correction codes have limited error correction capability, high algorithm complexity and large data redundancy. In this paper, a novel fault tolerance method for locating and correcting multiple bit errors in memory is proposed based on data similarity. The proposed method uses the inner product as the metric to analyze the similarity of the pre-protected data from the vertical and horizontal dimensions, respectively, and to construct the model of error location and correction. This method performs encoding and decoding in units of blocks and detecting and correcting in units of words, so it can correct any number of bits in a corrupted word with low redundancy overhead. Finally, irradiation tests were conducted on a commercial SRAM, and the feasibility of the proposed method is verified by using heavy ion ${}^{86}$Kr${}^{26+}$ as irradiation source.

Single Event Transients (SETs), i.e., voltage glitches induced in combinational logic as a result of the passage of energetic particles, represent an increasingly critical reliability threat for modern complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) employed in space missions. In rad-hard ICs implemented with standard digital cells, special design techniques should be applied to reduce the Soft Error Rate (SER) due to SETs. To this end, it is essential to consider the SET robustness of individual standard cells. Among the wide range of logic cells available in standard cell libraries, the standard delay cells (SDCs) implemented with the skew-sized inverters are exceptionally vulnerable to SETs. Namely, the SET pulses induced in these cells may be hundreds of picoseconds longer than those in other standard cells. In this work, an alternative design of a SDC based on two inverters and two decoupling capacitors is introduced. Electrical simulations have shown that the propagation delay and SET robustness of the proposed delay cell are strongly influenced by the transistor sizes and supply voltage, while the impact of temperature is moderate. The proposed design is more tolerant to SETs than the SDCs with skew-sized inverters, and occupies less area compared to the hardening configurations based on partial and complete duplication. Due to the low transistor count (only six transistors), the proposed delay cell could also be used as a SET filter.

In this work, reconfigurable Field Effect Transistor (RFET)-based ring oscillator (RO) has been proposed. RFET has two types of gates, control gate and program gate. This work investigates the possibility of exploiting the program gate of the RFET, for frequency tuning and duty cycle control using numerical device simulations. Different frequencies of operations have been demonstrated on the same oscillator by appropriately biasing the program gate. The program gates can also be used to control the duty cycle of the oscillator, at the given frequency. This paper also studies the single event effect (SEE) performance of the proposed RFET-RO. The simulation results suggest that the oscillators working at higher frequency are disturbed less compared to the oscillator working at lower frequency.

Single Event Transients (SETs) have become a major reliability concern for integrated circuits used in critical applications. Research to improve the radiation robustness of digital circuits has been conducted, assessing all abstraction levels (from the device up to the system). This study evaluates transistor-level radiation-hardened techniques in combinational logic, such as transistor folding, sizing and reordering. In addition, the efficiency of using supergates, including series-parallel and non-series-parallel CMOS structures, to harden the combinational logic is discussed. The dependence of input signals probability on a logic cell susceptibility to SET is assessed. Moreover, a new concept of electrical masking is introduced. The robustness of the investigated logic cells was evaluated regarding their SET rate. The CREME96 tool was used to generate the SET rates, and an electrical model was used to perform particle hit simulations. Obtained results have indicated that modifying the structure of logic gates can substantially improve circuit robustness without necessarily worsening its performance. Besides, using supergates in combinational logic design has demonstrated to be a promising hardening strategy. The most robust supergate implementation of a five-input logic function provided up to $28.1\%$ SET rate reduction regarding an approach based on standard cells, along with lower critical delay ($56.9\%$) and average power ($55.6\%$).

A new single-resistance-controlled-oscillator (SRCO) is presented which employs a single current feedback-operational amplifier (CFOA) along with four resistors but needs only a single external capacitor due to the incorporation of the CFOA-pole in the design. It provides independent control of the condition of oscillation and the frequency of oscillation through two separate resistors. To the best knowledge of the authors, this single-CFOA-based partially active-$R$ SRCO has not been reported explicitly in the technical literature earlier and hence is the fourth missing circuit of this class of SRCOs. Experimental results confirming the validity of the new proposition have been included and the comparative features of all the four circuits have been highlighted.

Focusing on the time domain optimization problem of an urban rail transit line, this paper constructs a passenger travel network with OD passenger flow data as input, by using a multi-path search algorithm based on dynamic cost to deduce the passenger space-time path. The passenger travel path is restored and the spatial and temporal distribution of passenger flow is calculated. Based on this, considering the influence of passenger flow spatial and temporal distribution on the time domain division, the orderly clustering method is used to optimize the time domain. Factoring in the influence of line capacity constraint, train running sequentially on time domain division and bidirectional time domain, a time domain optimization framework for an urban rail line is proposed in this study to integrate the time domain optimization results and improve the adaptability of optimization method. A practical line is taken as an example to verify the effectiveness of the proposed framework. Compared with the traditional time domain division method, the time domain division result accuracy is significantly improved and lays a foundation for the formulation of train service scheme which accurately matches transport capacity to demand.

This study presents two reconfigurable turbo/low-density parity-check (LDPC) decoding kernels for the two powerline communication standards, HomePlug and G.hn. Two architectures are presented, both of which use the radix-4 double-binary enhanced max-log maximum a posteriori probability algorithm with next-iteration initialization in turbo decoding. In LDPC decoding, the two architectures employ the normalized min-sum and the layered radix-4 forward and backward algorithms. The two algorithms cause differences in the architecture and throughput rate. Consequently, the proposed decoding kernels have different architectures when combined with the turbo decoding algorithm, and the two proposed decoding kernels each have their own advantages and disadvantages in terms of throughput and area cost. To make the features of two kernels more evident, we have implemented the proposed decoding kernels that lead to significant throughput gains and better area efficiency compared with other studies. The proposed decoding kernels can be operated in all modes specified in the HomePlug and G.hn standards using a 40-nm complementary metal-oxide-semiconductor (CMOS) process. Moreover, the proposed decoding kernels provide different solutions to achieve the expected throughput rates of the G.hn and HomePlug standards.

With the development of urbanization and the evolution of urban network systems, multimodal urban transport network (MUTN) systems play a vital role in improving network effects and operational efficiency. However, urban transport networks are easily affected by natural disasters and traffic incidents, which can lead to significant human and economic losses. Accordingly, it is vital to be able to assess the resilience of transport networks in the face of various disruptions. This study, therefore, utilizes complex network theory to analyze the resilience of multimodal urban transport networks, with the resilience accessed based on topological indices. The MUTN in Beijing is selected as a case study for simulation analysis. Based on the road network and subway network, a model MUTN is established, and the Monte Carlo method is used to simulate random attacks. The results show that the MUTN in Beijing has good resilience against disruptions. This study guides the evaluation of the overall resilience of multimodal urban transport networks and will be useful for transportation planners and decision-makers in dealing with emergencies and natural disasters in the future.

Nowadays, a computer-aided diagnosis system is required to monitor the cardiac patients continuously and detecting the heart diseases automatically. In this paper, a new field programmable gate array-based morphological feature extraction approach is proposed for electrocardiogram signal analysis. The proposed architecture is mainly based on the Generalized Synchrosqueezing transform but a detrended fluctuation analyzer is applied in the reconstruction stage for capturing the maximum information of QRS complexes and P-waves by eliminating a set of noisy intrinsic modes. Then, a correntropy envelope is determined from the QRS enhanced signal for localizing the QRS region accurately. Also, an adaptive heuristic framework is introduced to detect the true P-wave from the P-wave enhanced reconstructed signal by analyzing both the positive and negative amplitudes. In addition, a root mean square Error estimation-based adaptive thresholding approach is used to estimate the T-wave after removing the P-QRS complexes. The proposed architecture has been implemented on field programmable gate array using the Xilinx Vertex 7 platform. The performance of the proposed architecture is validated by performing a comparative study between the resultant performances and those attained with state-of-the-art feature descriptors, in terms of Sensitivity, accuracy, positive prediction, error rate and field programmable gate array resources estimation. The proposed sensitivity, accuracy and positive prediction are 99.84%, 99.85% and 99.86% for QRS detection approach. The proposed sensitivity, accuracy and positive prediction are 99.45%, 99.23% and 99.78% for P-wave detection approach. The proposed sensitivity, accuracy and positive prediction are 99.58%, 99.65% and 100% for T-wave detection approach. The simulation results show that the proposed architecture overtakes existing designs and minimizes hardware complexity, which proves the suitability of this approach on real-time applications of electrocardiogram signals.

With the wide application of data mining and deep learning in mobile cellular network operation and maintenance, network measurement report (MR) plays an increasingly important role in artificial intelligence for IT operations (AIOps). For the integrity of MR reported by the operation and maintenance (OM) proxy of base station, existing collecting methods are typically based on static distributed clustering. Due to the lack of effective load balancing scheme, nevertheless, these methods typically result in some issues, e.g., low collecting efficiency, poor scalability, and excessive number of servers. Thus, in this work, leveraging the historical law of uploading MR for load forecasting, we propose the weighted least-connection load balancing algorithm (LPWLC) based on load forecasting. First, the historical law of reported MR is utilized to predict the load. Second, using the strategy of static binding and dynamic load adjustment, we bind OM with the assigned server in one cycle, calculate the server load in real-time, and evaluate the server weight by the load of each server. Finally, real-time load adjustment is carried out in line with the number of request connections and the weight of servers. Compared with the existing ones, the proposed algorithm could remove backup servers, thereby effectively reducing the cost and power consumption. Compared with the existing methods, this method has improved the load balancing degree by 28%, and reduced the energy consumption by 104W per hour.

Federated Learning (FL) enables multiple parties to train a global model collaboratively without sharing local data. However, a key challenge of FL is data distribution heterogeneity across participants, which causes model drift in local training and significantly reduces the model performance. To address this challenge, we analyze the inconsistency differences between different model layers of local models and further propose Layer-wise Distance Regularization (LWDR) and Layer-wise Momentum Aggregation (LWMA). The proposed LWDR and LWMA optimize the local training and model aggregation processes, respectively, to improve the convergence performance of FL on data in the nonindependent and identically distributed (Non-IID) scenarios. Our experiments on well-known datasets show that our algorithm significantly outperforms the state-of-the-art FL algorithms in convergence speed, accuracy, and stability in different Non-IID scenarios.

In downlink multiple-input, multiple-output, (MIMO) and non-orthogonal multiple access (NOMA) systems, the inter-cluster interference can be cancelled by optimizing pre-coding and detection matrices. Thus, the MIMO-NOMA channel is decomposed into multiple single-input, single-output and (SISO)-MOMA channels. Then, we formulate an energy efficiency (EE) optimization problem subject to the signal-to-interference-plus-noise ratio (SINR) constraints which is non-convex. To solve the problem, we propose the algorithm based on one-dimensional linear search and first-order Taylor expansion. Moreover, as in conventional communication systems, EE and spectrum efficiency (SE) cannot always be improved simultaneously. Thus, the trade-off between EE and SE is investigated based on the formulated problem. Numerical analyses and simulation results verify the proposed algorithm. In addition, the performance in terms of EE and the EE-SE trade-off can be improved by optimizing the user pairing method.

This work aims to establish an optimal design of the Smith dead-time compensator for a nonsquare multivariable system with a transfer function matrix containing first-order dead time elements. The scheme has a set point tracking controller along with disturbance rejection using an optimal estimator. An inverse signal from the estimator eliminates the disturbance. The proposed method significantly improves the disturbance rejection and performance index compared to the other established methods. The common evolutionary algorithms such as the grey wolf optimization technique and teaching learning based algorithm have been used to tune the controllers.

The system environments are built with extensible, flexible, extensible and feature-rich platforms that provide consumers with the benefits of several services, applications and devices. However, the evolution of the internet and shared networks has changed the computing systems more vulnerable to attacks based on the operating system, software and hardware levels. Due to this, there is a growing need to ensure the software and hardware platforms are being secured from viruses or other unauthorized operations. In this paper, a new Hardware-based built-in security module has been proposed in System on Chip (SoC) without loss of productivity and system slowdown. The proposed process integrates a Hardware security module within the SoC, and it establishes higher visibility and controllability of the SoC than achieved from an external device. First, the proposed method allows the SoC to check without dependency on other unsecured elements within the system. Then, the method can examine some components within the SoC on its own to test from time-to-time that no unauthorized access or attempts to bypass the integrity of the system or SoC has been made. After, it allows the SoC to be controlled without any dependency on other unsecured components or communication via unsecured external interfaces. IxChariot is used to carry out the performance test, and then the hardware-based security is proved using Atheros Mini PCIeXB112 cards. As a result, better TCP throughputs of 571, 571 and 604 have been determined in normal mode, and in burst mode, 580, 572 and 619 throughputs have been determined. Finally, the security hardware provides security without system slowdown or lost productivity and burdening the host processor.