Journal of Circuits, Systems and Computers

Battlefield of Things (BoT) is a modern defense network that connects smart military devices to strategic networks. Cybersecurity plays a vital role in maintaining the security of BoT networks and provides encrypted communication networks with combat devices on an end-to-end or peer-to-peer basis. This paper proposes approaches to BoT networks that operate on a three-tier architecture, starting with an application and service layer, a network and cybersecurity layer, and finally, a battlefield layer; implements CNN-YOLO-based target detection; and also formulates information security policies, privacy, and IT laws to maintain algorithmic data access and authorization. It connects a battlefield combat equipment network to a command data center’s ground base station wireless, Bluetooth, sensor, radio, and ethernet cable. This paper analyzes prior Internet of Things (IoT) device attack strategies by collecting data sets of IoT security breaches from external sources. How the system security works, what breach techniques an attacker can use, how to avoid these, and how our systems can be strengthened to protect us from future attacks are discussed in detail.

Improved speed, reduced delay, reduced size and reduced power are the most important requirements of integrated circuits. The carry select adder (CSA) is one of the most important adders in most data processors for performing arithmetic operations. The speed of parallel adders can be enhanced CSA, which widens the area to speed and eliminates propagation delays. The major problem faced in CSA is inefficient area due to the usage of multiple pairs of Ripple carry adders (RCAs) for generating the sums and carry. This research paper proposes the modified 32-bit square root carry select adder (MSCSLA) to improve the direct digital synthesizer’s performance (DDS). DDS plays an effective role in the digital system due to its ability of broad frequency generation. Phase accumulator is the main component in the DDS synthesizer, where the speed of the adder is enhanced through MSCSLA. The general square root CSA still consumes more power due to the assembly of more RCAs. Hence, in the proposed approach, certain sets of RCAs are replaced with BEC1 (Binary to excess 1 convertor) to improve the speed and reduce the delay of the adder. Finally, the continuous sinusoidal waveform is attained by attenuating the high-frequency components by adopting a low pass filter. The entire structure of DDS is designed using Xilinx Verilog coding. The Simulation result shows better outcomes in terms of area, delay, power, and high performance in the DDS synthesizer compared to the existing CSAs. When compared to the existing adders, the area occupied by the proposed MSCSLA model is attained to be 636$\mu$m², the power is achieved as 50.125$\mu$W and delay is attained to be 1.280ns, which are comparatively less. When comparing delay and maximum frequency with the existing techniques, the proposed model obtained minimum delay and maximum frequency. The overall power consumption by the proposed model is also attained to be lower than the existing techniques.

Based on the analysis of the reasons, principles and classification of fuzzy set data calibration, we analyze that the fuzzy set data calibration membership is influenced by different data distribution, the crossover anchored points setting and transformation selection. Starting from the common problems existing in the current fuzzy-set qualitative comparative analysis (fsQCA) application research, this paper analyzes the possible reasons for ignoring the data calibration research, divides the relationship between the three dimensions of original data distribution, the crossover anchored points setting and calibration transformation and data calibration, and makes a visual analysis on their influence relationship through simulated data. Data distribution, crossover points anchored setting and transformation selection all have a significant impact on fsQCA calibration membership. The distribution of the original data will be a skew attribute consistent with the calibration membership. The cross combination of the high, medium and low setting of the crossover points and the selection of the calibration transformation will produce a significantly different calibration membership, and the crossover points anchored setting has a more obvious impact on the calibration membership than the selection of the calibration transformation.

In this paper, a novel complementary metal-oxide semiconductor (CMOS) transistors based first-order voltage-mode all-pass filter is proposed. The filter circuit employs six metal-oxide semiconductor (MOS) transistors and minimal number of passive components, i.e., a resistor and a capacitor. The core of the proposed filter is a CMOS inverting amplifier with unity gain. The proposed circuit exhibits some attractive features such as compact design, high input impedance and ability to provide non-inverting and inverting all-pass responses simultaneously. Additionally, it does not require any kind of passive element matching constraints. Furthermore, by replacing the passive resistor with an active negative channel metal-oxide semiconductor (NMOS) transistor, the proposed filter is enriched with the much-desired feature of tunability. The theoretical behavior is tested and demonstrated by carrying SPICE simulations using TSMC 0.18$\mu$m level-7 CMOS process parameters.

In this paper, a current-mode (CM) proportional integral derivative (PID) controller based on second-generation voltage conveyor (VCII) is presented. The proposed circuit consists of two-plus type VCIIs, two resistors, and two capacitors. There is no need of critical matching condition. Considering the parasitic impedance, the operating frequency ranges of the proposed PID network are examined. The magnitude and phase responses, Monte Carlo, temperature and input-output noise analyses have been simulated. The simulation results are obtained with the LTspice program using AD844 SPICE macro-model under $\pm$9V DC supply voltages. The total power consumption of the proposed CM PID controller is 235mW.

Multimedia, machine learning and deep learning applications have a significant constraint on power consumption. A multiplier is a crucial component for many error-aware applications. An efficient approximate computing scheme is used for the error-tolerant applications due to higher accuracy in power cases. In the Booth, multiplier approximation is implemented for partial product generation and accumulations network. The significant stage of a multiplier is accumulation. In this paper, an efficient accumulation stage is suggested for the Radix-4 and 8-bit approximate Booth multiplier. The proposed accumulation multiplier has high speed, minimum area, negligible path delay and low power consumption. Compared to the Booth multiplier design with modified Booth encoding and conventional carry look-ahead adder for product generation with no other error, the proposed 8-bit multiplier design-I reduced power consumption, area and delay a maximum of 13.7%, 8.4% and 19.8%, respectively. Also, our proposed design is compared with the design of Booth multiplier with approximate Booth encoding and conventional carry look-ahead adder for product generation. The proposed 8-bit multiplier design-II reduced power consumption, area and delay by a maximum of 38.2%, 28.3% and 13.7%, respectively.

Due to the open-source and versatility of the Android operating system, Android malware has exploded, and the malware detection of Android IoT devices has become a research hotspot in recent years. Static analysis technology cannot effectively analyze obfuscated malware. Without decomposing, the existing detection methods are mainly based on grayscale images and single files without analyzing and verifying their anti-obfuscation performance. In addition, the current detection of Android malware using deep learning is concentrated in the field of binary classification. This paper proposes a multi-classification method of the Android malware family based on multi-class feature files and RGB images to solve these problems. The method proposed in this paper does not need to decompile the Android APK installation package. However, it extracts the DEX file and XML file in batch from the APK installation package. Then, it converts the file into an RGB image using the conversion algorithm that converts Android software into images. Finally, the deep neural network automatically obtains the RGB image texture features to realize the multiple classifications of the Android malware family. Experimental data show that the proposed method has high detection performance, and the accuracy of multiple classifications of the Android malware family is as high as 99.84%. In addition, the method based on RGB image is better than the grayscale image in detection accuracy, and the effect of RGB image combined with DEX and XML is better than that of separate DEX file image and separate XML file image. Therefore, the method proposed in this paper can effectively detect the obfuscated Android malware, and the detection accuracy of 99.23% can be achieved for the obfuscated sample data. Furthermore, this method has good anti-obfuscation ability. The proposed method is compared with those based on Multi-Layer Perceptron, Long Short-Term Memory, bidirectional Long Short-Term Memory and Deep Belief Network. The experimental results show the proposed method’s effectiveness and high generalization performance.

This paper demonstrates an energy-efficient implementation of piecewise polynomial approximation to evaluate the complex functions of graphical processing units (GPUs). A novel approach is employed to implement the first-order piecewise approximation serially which leads to high savings in power and area. Dual channel multiplier (DCM) scheme is proposed to simplify the hardware architecture of the piecewise polynomial approximation. The proposed methodology is implemented with 90nm CMOS technology and it can perform different complex functions using a simple multiplier hardware structure. DCM achieves improvement in energy saving by up to 81% at a penalty cost of 10 clock cycles. Simulation results confirm that this work attains at least 83%, and 55% saving in power and area as compared to the traditional techniques, respectively. The proposed methodology can implement any degree of the piecewise polynomial approximation utilizing the DCM.

Digital microfluidic biochips (DMFBs) are emerging as an alternative to the cumbersome traditional laboratories for biochemical analysis. DMFBs come under micro-electro-mechanical systems and are a class of lab-on-a-chip devices. DMFBs provide automation, miniaturization and software programmability. The droplet routing algorithm determines concurrent routes for a set of droplets from their source cells to individual target cells on a DMFB. In this paper, a double deep Q-network (DDQN)-based droplet routing algorithm has been proposed. DDQN is a temporal difference-based deep reinforcement algorithm that combines Double Q-learning with a deep neural network algorithm. In the proposed work, routes for droplets are determined by DDQN, and later collisions are resolved using stalling and/or detouring. The latest arrival time of droplets arriving last at its target and cell utilization is taken as objectives for routing algorithm performance evaluation. The proposed method is evaluated on two standard benchmark suites. Simulation results show that the proposed DDQN-based droplet routing algorithm produces competitive results compared to state-of-the-art algorithms.

This work presents a fully integrated mixed-mode low-dropout voltage regulator that achieves a fast transient response by utilizing two feedback mechanisms. The first feedback mechanism is the conventional analog regulation that includes an operational amplifier. The second feedback mechanism is based on digitizing any fast change in the output voltage using multiple comparators and subsequently enabling either an NMOS-based or a PMOS-based current DAC. The DAC provides current in opposite polarity to the sharp transient change in load current. As a result, addressing sharp changes in load current is not limited by the gain–bandwidth product of the error amplifier. The LDO was implemented using 180-nm CMOS technology devices. It uses a supply voltage input range of 1.6–2V and produces an output voltage of 1.2V. In simulations, the LDO regulator achieves 143-$\mu$ A quiescent current, $-$56-dB PSRR @ 1-kHz noise frequency and an output voltage drop of around 200mV for a load current step of 100mA. The LDO can provide a maximum load current of 200mA.

Solar PV-connected distributed utility grid often faces several issues due to variable penetration of the generated power. It creates frequent disturbance in load side and increases the voltage instability. It is a great challenge to maintain the stability at distributed low-voltage grid and improve the quality of power. In order to overcome this problem, this paper proposes an adaptive voltage and current regulatory approach to improve the power quality in a solar PV-integrated low-voltage utility grid. It supplies auto-adjustable reactive power during the small and large voltage deviations in the grid. The proposed approach assures that the load bus voltage is maintained at 1 p.u. under variable environmental conditions. In addition, the power quality gets improved by injecting the power with improved quality. Three cases of standalone mode, grid-connected modes with and without STATCOM have been investigated and reported in this paper. To validate the proposed adaptive voltage and current regulatory approach, the dynamic results of regulated grid voltage under poor environmental conditions are analyzed and the measured results are presented in this paper. Furthermore, the obtained results are evaluated with the existing approaches such as BAT, firefly and elephant herding optimization (EHO) algorithms and reported in this paper.

Malicious attacks to software applications are on the rise as more people use Internet of things (IoT) devices and high-speed internet. When a software system crash happens caused by malicious action, a malware imaging method can examine the application. In this study, we present a novel malware classification method that captures suspected operations in a variety of discrete size image features, allowing us to identify such IoT device malware families. To decrease deep neural network training time, essential local and global image features are selected using a combined local and global feature descriptor (LBP-GLCM). The classification performance of the proposed deep learning model is improved by combining the predictions of weak learners (CNNs) and using them as knowledge input to a multi-layer perceptron meta learner. This is a neural network ensemble with stacked generalization that is used to improve network generalization ability. The public dataset used for performance evaluation contains 5472 samples from 11 different malware families. In order to compare the proposed methodology to current malware detection systems, we developed a baseline experiment. The proposed approach improved malware classification results to 98.5% accuracy and 98.4% accuracy when using $256\times 256$ and $200\times 200$ image sizes, respectively. Overall, the results showed that the stacked generalization ensemble with multi-step extracting features is a more effective method for classification performance and response time.

Several nonterminal nodes in the ad-hoc sensor network architecture are involved in effectively communicating data. There are not enough nodes other than the terminals to process sensor data and send it between nodes. Because of this, the exchange of sensor data relies on devices capable of predicting events and responding quickly. Identifying the cluster head is essential to the network’s long-term viability and operational efficiency. This paper proposes a robust probabilistic buckshot approach to identify the appropriate nodes, and the smooth handover mechanism in the corresponding cycles is mechanized. The proposed model also employs a heuristic algorithm named HARIS to identify the best cluster head by analyzing the residual energy associated with each sensor node over multiple iterations. The data exchanged among the nodes is encrypted using a lightweight accumulative data encryption model to ensure the confidentiality of the data. The proposed model is evaluated using various statistical analysis metrics like node availability, computational delay, throughput, and network lifetime. The proposed model outperforms the existing energy-sensitive sensor network models by 20–23%.

A new decoding scheme aided by simulated annealing algorithm is proposed to further improve the decoding performance of successive cancellation (SC) for polar codes at the short block. We use simulated annealing to revise the decoding result of SC which cannot pass the CRC check. To generate the new neighbors, the decoder flips one bit from the set of the least unreliable information bits each time in the estimated source vector of SC decoding. Euclidean distance is used to measure the gap between the new neighbor solution and the received word so that the decoder can obtain a global optimal solution. Simulation shows that the proposed decoder has a performance gain about 0.5 dB in terms of frame error rate (FER) under short blocks in the additive white Gaussian noise (AWGN) channel compared to other basic decoders, while keeping a low time cost through a parameter tuning process.

This paper presents design and analysis of a beam switchable $1\times 2$ array patch antenna fed by a $2\times 2$ Butler matrix based hybrid coupler for 2.45GHz radio frequency identification (RFID) reader applications in the ISM band. The proposed beam switchable array antenna arrangement consists of two identical patch elements, a pleated quarter-wavelength impedance transformer (PQWIT), and a hybrid coupler. The concept of PQWIT has been utilized to reduce the overall implementation area of the patch elements. The overall area of the patch element is miniaturized by 50% due to the implementation of PQWIT. This miniaturized antenna is used as a radiating element for designing a beam switchable $1\times 2$ array antenna fed by a hybrid coupler. The proposed antenna prototype has been fabricated on a 1.56mm thick Rogers RT/duroid 5880 substrate with a physical area of $112\times 100$mm². The simulation and measured results exhibit good agreements. The designed antenna offers a broad bandwidth of 844MHz (1.956–2.80GHz), peak gain of 8.86 dB, peak radiation efficiency of 99.52% and has two switchable beams in the directions $-30^{\circ }$ and $+30^{\circ }$. The suggested switched beam array antenna is suitable for RFID reader applications at 2.45GHz for tracking of moving objects.

Aiming at the fully differential (FD) sensing and high-precision small-signal output characteristics of micro-electromechanical systems (MEMS) gyroscopes, a low area overhead, high-gain, medium-speed, FD operation amplifier (Op-Amp) is designed for building a small-signal processing delta-Sigma analog-to-digital converter (ADC). The Op-Amp is a two-stage cascade structure, which combines folded cascade (FC) and gain-boosted technology to make the low frequency gain up to 129 dB, to meet the high-precision requirements of 18-bit delta-Sigma ADC. The first stage is FC gain-boosted structure, which uses a small bias current to achieve high-gain and low area overhead. In order to reduce the input noise, process smaller signals, the input pair adopts positive channel Metal–Oxide–Semiconductor (PMOS). The second-stage uses a large bias current to achieve a high unity gain bandwidth (UGB). Under the premise that the tail current source of the first stage is PMOS, in order to reduce the area overhead, abandoning the traditional common source (CS) structure of negative channel Metal–Oxide–Semiconductor (NMOS) input and PMOS as the current mirror load, adopting a new CS structure that PMOS input and NMOS used as independent bias current source. In this structure, the large overdrive voltage significantly reduces the size of transistors and greatly reduces the area overhead. The Op-Amp was implemented in SMIC 0.18 μm BCD process, 5 V supply voltage. Its post-layout simulation achieved a low-frequency gain of 129 dB, a UGB of 35 MHz and a phase margin (PM) of 62° for a load capacitance of 2 pF. Output voltage swings are ±3.71 V and including common mode feedback (CMFB), bias voltage generating circuit and filter capacitor, the area of Op-Amp is 167.162 μm × 200.82 μm. Behavioral-level verification shows that the designed Op-Amp meets the requirements of high-precision delta-Sigma ADCs.

This paper presents a predictive noise shaping (NS) Successive Approximation (SAR) Analog-to-Digital Converter (ADC), which improves its conversion speed by 25%, compared to its counterpart with 0.3% less redundancy. It begins by investigating the Signal to Noise and Distortion Ratio (SNDR) degradation when using a lower Oversampling Ratio (OSR, e.g., 8) than required in the prior state-of-the-art works, when predicting the first 4 MSBs with a second-order predictor. Later, it compares the SNDR for the same predictor with and without the bit weight redundancy in the capacitor array. In addition, designs with various levels of redundancies and OSRs are compared on their SNDRs. Both MATLAB and Cadence simulation results verified that by introducing 0.3% more redundant bit weight, either 8 dB more SNDR at the same bandwidth, or 25% speed improvement can be obtained while maintaining its SNDR.

Electric vehicles play a key role in the transition to an environmental-friendly transportation system and can meanwhile enhance the power system’s evolution to the smart grid. With the adoption of dynamic pricing and usage scheduling enabled by the smart grid equipment, a variety of smart charging strategies have been designed to make the most of flexibility contained in their considerable electricity demand, whereas less effort is devoted to users’ willingness to participate. In this paper, we model a noncooperative pricing game between two types of charging stations. One offers conventional fast charging and the other uses the electric vehicles’ onboard batteries to provide regulation service to the grid. With drivers’ risk attitudes and bounded rationality taken into consideration, we design a prospect theory-based decision model to calculate the proportion of users that would go for the regulation-providing charging option. The decision model of the customer base is a critical determinant of profitability and it enables two competitors to strategically set their prices that optimally balance between gaining in market share and growing in profit per client. We prove the existence of a pure strategy Nash equilibrium for the game proposed and compute the equilibrium prices in different circumstances with respect to market settings and user segments. A comprehensive analysis of the results gives insights into the key factors at play and provides the grid operators with indications of how to increase the penetration of electric vehicles in the ancillary service market.