Journal of Circuits, Systems and Computers

Coronavirus disease-19 (COVID-19), an infectious disease that spreads when people live in close proximity has greatly impacted healthcare systems worldwide. The pandemic has so disrupted human life economically and socially that the scientific community has been impelled to devise a solution that assists in the diagnosis, prevention and outbreak prediction of COVID-19. This has generated an enormous quantum of unstructured data that cannot be processed by traditional methods. To alleviate COVID-19 threat and to process these unstructured data, big data analytics can be used. The main objective of this paper is to present a multidimensional survey on open source datasets, techniques and tools in big data to fight COVID-19. To this end, state-of-the-art articles have been analyzed, qualitatively and quantitatively, to put together a body of work in the prediction of COVID-19. The findings of this review show that machine learning classification algorithms in big data analytics helps design a predictive model for COVID-19 using the open source datasets. This survey may serve as a starting point to enhance the research in COVID-19.

Thanks to its capability of providing seamless massive access and extended coverage, satellite communication has been envisioned as a promising complementary part of the future 6G network. Due to the large satellite-to-ground propagation loss, noise mitigation is one of the most important considerations for implementing key interface technologies on boarding a satellite, e.g., random access (RA). This paper aims at developing an effective preamble detection method with noise suppression for 5G-ntegrated satellite RA systems. Specifically, according to the satellite ephemeris and user equipment location, we first perform the pre-compensation of timing and frequency offset before preamble transmission to determine all the possible correlation peak positions in advance. By leveraging the advantage of the wavelet transform in signal-to-noise separation, we further design a novel detection framework based on wavelet denoising, which can efficiently reconstruct preamble signature from the noisy power delay profile. Simulation results validate the feasibility of the proposed method, and show that our method can achieve a notably improved detection performance under extremely low signal-to-noise ratio conditions, in comparison with the conventional one.

The proposed system provides an energy management method for various types of an energy storage system including cascade utilization battery. The method is used to receive, store and manage the relevant operating data from the energy storage battery and also randomly determine the energy distribution coefficient of the energy storage battery. According to the adaptive energy distribution method, the power value of the total distributed energy storage power to the cascade utilization energy is calculated and also the energy distribution coefficient of the energy storage battery in real time is adjusted. Finally, the corrected command value of the energy storage battery power is obtained as an output. The system can not only prevent overcharging and over-discharging of the energy storage system, but also maintain the good performance of the energy storage system. To realize the coordinated control and energy management of the battery power plant, we use multiple types, including conventional battery and cascade utilization power battery control purpose. The performance metrics, namely, real-time energy management, computational time and operating cost are employed for the experimental purpose. The simulation results show the superior performance of the proposed energy management system over other state-of-the-art methods.

This paper proposes an improved two-stage and four-stage CMOS ring-Voltage Controlled Oscillator (VCO) design with large frequency at output, improved phase noise, and reduced consumption of power. A PMOS varactor is used in conventional circuit to obtain high tuning-range and very low consumption of power. Cadence Virtuoso 90 nm technology was used to simulate this differential ring-VCO with the proposed dual input differential delay cell. This two-stage and four-stage design gives wider range of tuning from 1.254 to 6.694 GHz (81.26%) and 1.821 to 5.259 GHz (65.37%), respectively, with the change in $V_c$ from 0.1 to 1 V. The power-consumption of two-stage ring VCO and four-stage ring VCO varies from 48.02 to 89.33 $\mu \mathrm{\text{W}}$ and 66.81 to 157.02 $\mu \mathrm{\text{W}}$ respectively. The proposed two-stage and four-stage VCO exhibits −114.46 and −111.06 dBc/Hz at 1 MHz offset from 6.694 and 5.259 GHz carrier frequency, respectively. The proposed two-stage and four-stage differential ring-VCO results in wider tuning range and very low consumption of power and an improved figure of merit and phase-noise.

This paper realizes the implementation of Improved Multi-objective Mayfly Algorithm (IMOMA) for getting optimal solutions related to optimal power flow problem with smooth and nonsmooth fuel cost coefficients. It is performed by considering Simulated Binary Crossover, polynomial mutation and dynamic crowding distance in the existing Multi-objective Mayfly Algorithm. The optimal power flow problem is formulated as a Multi-objective Optimization Problem that consists of different objective functions, viz. fuel cost with/ without valve point loading effect, active power losses, voltage deviation and voltage stability. The performance of Improved Multi-objective Mayfly Algorithm is interpreted in terms of the present Multi-objective Mayfly Algorithm and Nondominated Sorting Genetic Algorithm-II. The algorithms are applied under different operating scenarios of the IEEE 30-bus test system, 62-bus Indian utility system and IEEE 118-bus test system with different combinations of objective functions. The obtained Pareto fronts achieved through the implementation of Improved Multi-objective Mayfly Algorithm, Multi-objective Mayfly Algorithm and Nondominated Sorting Genetic Algorithm-II are compared with the reference Pareto front attained by using weighted sum method based on the Covariance Matrix-adapted Evolution Strategy method. The performances of these algorithms are individually analyzed and validated by considering the performance metrics such as convergence, divergence, generational distance, inverted generational distance, minimum spacing, spread and spacing. The best compromising solution is achieved by implementing the Technique for Order of Preference by Similarity to Ideal Solution method. The overall result has shown the effectiveness of Improved Multi-objective Mayfly Algorithm for solving multi-objective optimal power flow problem.

In response to the continuous sophistication of cyber threat actors, it is imperative to make the best use of cyber threat intelligence converted from structured or semi-structured data and Named Entity Recognition (NER) techniques that contribute to extracting critical cyber threat intelligence. To promote the NER research in Cyber Threat Intelligence (CTI) domain, we provide a Large Dataset for NER in Cyber Threat Intelligence (LDNCTI). On the LDNCTI corpus, we investigated the feasibility of mainstream transformer-based models in CTI domain. To settle the problem of unbalanced label distribution, we introduce a transformer-based model with a Triplet Loss based on metric learning and Sorted Gradient harmonizing mechanism (TSGL). Our experimental results show that the LDNCTI well represents critical threat intelligence and that our transformer-based model with the new loss function outperforms previous schemes on the Dataset for NER in Threat Intelligence (DNRTI) and the dataset for NER in Advanced Persistent Threats (APTNER).

In the past 20 years, semiconductor manufacturing technology has advanced rapidly, but the advancement of integrated circuit (IC) testers has been slow. Using obsolete testers to inspect advanced wafers has become a significant challenge for test manufacturers. In this research, we used DITM (digital IC testing model) to discuss the impact of the test guardband (TGB) on quality and yield. Considering the interaction between semiconductor fabrication capability parameters and test capability parameters, we proposed an estimation method [deductive estimation method (DEM)] to analyze the electrical distribution changes of products after chip production and deduce the yield of future products. The deductive estimation method can correctly depict the future test yield $(Y_t)$ curve using the chip frequency data published by IRDS (International Roadmap for Devices and Systems) in 2017. Furthermore, test manufacturers can measure whether the current test capabilities can cope with future semiconductor chip manufacturing capabilities by predicting the trends. Next, test manufacturers can maintain high-quality and high-yield chip output by pre-adjusting the hardware testing capabilities of ATE (automated test equipment) or proposing more effective chip testing methods.

Action recognition is a challenging task of modeling both spatial and temporal context. Numerous works focus on architectures modality and successfully make worthy progress on this task. While due to the redundancy in time and the limit of computation resources, several works focus on the efficiency study like frame sampling, some for untrimmed videos, and some for trimmed videos. With the intent of improving the effectiveness of action recognition, we propose a novel Computational Spatiotemporal Selector (CSS) to refine and reinforce the key frames with discriminative information in video. Specifically, CSS includes two modules: Temporal Adaptive Sampling (TAS) module and Spatial Frame Resolution (SFR) module. The former can refine the key frames in the temporal space for capturing the key motion information, while the latter can further zoom out some refined frames in the spatial space for eliminating the discrimination-irrelevant structural information. The proposed CSS is flexible to be embedded into most representative action recognition models. Experiments on two challenging action recognition benchmarks, i.e., ActivityNet1.3 and UCF101, show that the proposed CSS improves the performance over most existing models, not only on trimmed videos but also untrimmed videos.

In the direct current (DC) microgrid, a communication-less control algorithm to keep a stable state of the isolated DC microgrid is presented in this paper. In order to get balance of the state of charge (SoC) among multiple battery energy storage systems (BESs), a control algorithm with adaptive droop coefficient is proposed. When the SoC of BESs has a deviation, the droop coefficient will change with the SoC. The DC bus voltage is kept at a stable value within a small range of deviation using the proposed adaptive control algorithm, thus improving the voltage quality. The coordinated control strategy is significant to keep the system stable and to ensure the power balance of the DC microgrid. Finally, several representative cases are discussed and verified. The simulation results show that the DC bus voltage regulation has better stability and robustness without communication and the proposed control algorithm has a desirable performance on the balance of the SoC.

Intelligent agriculture has become the development trend of agriculture in the future, and it has a wide range of research and application scenarios. Using machine learning to complete basic tasks for people has become a reality, and this ability is also used in machine vision. In order to save the time in the fruit picking process and reduce the cost of labor, the robot is used to achieve the automatic picking in the orchard environment. Cherry target detection algorithms based on deep learning are proposed to identify and pick cherries. However, most of the existing methods are aimed at relatively sparse fruits and cannot solve the detection problem of small and dense fruits. In this paper, we propose a cherry detection model based on YOLOv5s. First, the shallow feature information is enhanced by convolving the feature maps sampled by two times down in BackBone layer of the original network model to the input end of the second and third CSP modules. In addition, the depth of CSP module is adjusted and RFB module is added in feature extraction stage to enhance feature extraction capability. Finally, Soft- Non-Maximum Suppression (Soft-NMS) is used to minimize the target loss caused by occlusion. We test the performance of the model, and the results show that the improved YOLOv5s-cherry model has the best detection performance for small and dense cherry detection, which is conducive to intelligent picking.

Monocular depth estimation aims at inferring three-dimensional (3D) cues from a single RGB image. Although existing methods have achieved a certain degree of success, the impact of redundant information has rarely been studied. We propose to improve estimation accuracy by implicitly eliminating redundant information. To this end, we creatively apply discrete representation to monocular depth estimation. By mapping continuous variables into the corresponding learning-based discrete latent space, a hierarchical multi-scale latent map is acquired as the decoder input. Removing redundant information can enhance prediction performance by making the depth estimator balance the local and global. Furthermore, to fully take advantage of the discrete representation, a lightweight fusion mechanism is introduced to aggregate information in multi-scale feature maps.Experiments on NYU Depth V2 dataset demonstrate that our network is competitive with the state of the arts.

This paper demonstrates a low power, frequency compensated with on-chip capacitor, low dropout linear voltage regulator. The proposed low dropout regulator (LDO) delivers a constant output voltage of 2.4V for an input range of 2.5–6.8V. A minimal drop of 2mV and 20mV was observed at no load and full load output current of 0 A to 100mA, respectively. LDO is realized by a high-gain two-stage error amplifier, internally compensated by passive a high-pass filter to achieve stability over a load current range of 0–100mA without occupying as much area as an active high-pass filter. The LDO presented requires a bias current of 10mA with a reference voltage of 1.5V and is designed in 180-nm technology.

The objective is to produce a high-gain DC to DC flyback boost converter integrated with a multi-level converter for inverter applications. It has two stages: the first one is flyback multilevel converter, and another level comprises level controller and H-Bridge Inverter. The addition of voltage multiplier cells enhances the commercial flyback converter with multiple voltage outputs producing high voltage gain. These multiple outputs are fed to an H-bridge inverter for producing a multilevel output in an inverter. This DC-to-DC converter steps up the DC supply, but it also decreases the switches, diodes, and capacitors. This kind of converter not only reduces the switch count but also reduces the voltage stress, and total harmonic distortion. To increase the number of levels in the converter, the number of capacitors and diodes in the DC-to-DC converter without disturbing the main circuit must be increased to achieve the required output voltage. The number of power switches for the proposed topology is compared to comparable topologies in the current literature. The results of the simulation are communicated via the MATLAB/ Simulink domain, and the recommended converter’s functionality is demonstrated.

In this paper, we propose a rate control (RC) scheme for versatile video coding (VVC) to enhance coding performance. First, we propose a rate–distortion (R–D) model at the coding tree unit (CTU) level to describe the R–D relationship. Second, we adjust the quantization parameter (QP) and Lagrange multiplier at the coding unit (CU) level according to visual features to improve the rationality of local coding results. Finally, we propose a model parameter updating strategy to guarantee bitrate accuracy. The experimental results demonstrate that our RC method has better R–D performance with similar bitrate accuracy and better visual quality compared to the default RC strategy in VVC reference software VTM 10.2.

The object of this paper is to introduce a new CMOS differential input single output (DISO) transconductor (realizable from eight MOSFETs operating in saturation) and a dual input dual output (DIDO) transconductor (realizable with 16 MOSFETs operating in saturation) and their applications in realizing grounded/ floating, positive/ negative, electronically controllable resistors and inductors. The workability of all the prepositions has been demostrated by SPICE simulations using TSMC 0.18$\mu$ m CMOS technology parameters. The paper, thus, adds a number of useful electronically-controllable circuits to the existing repertoire of CMOS analog circuits for signal processing.

The demand for high-speed and energy-efficient adders in modern portable applications has drastically increased in recent decades. The existing adders have achieved high speed due to their parallel prefix structure, but it consumes more power for wide operands. The proposed Hybrid Brent Kung-Modified Sum Generator (HBK-MSG) achieved high speed due to the usage of Brent Kung (BK) adder and consumes low power with the help of MSG unit. This hybrid adder architecture is applicable for larger operands. It also uses two different structures of sum generators which compute the added result of the operands by incorporating the complement of the carriers. It is designed and simulated using Xilinx ISE 13.2 and it is coded in Verilog HDL. The performance of the proposed HBK-MSG adder is analyzed by measuring area, delay and power consumption. The proposed 64-bit HBK MSG adder reduces the energy consumption by 62.98%, 48.05%, 33.09%, 28.12% and delay by 63.54%, 48.46%, 34.58%, 28.15% when compared with the existing adder designs such as RCA, CSLA, PPF/CSSA_4 and hybrid adder.

The neuristor based on memristors can be used to mimic synapse and neurons of biological neural systems, and it is the key unit of spiking neural networks. However, the resistance states of realistic memristors are nonvolatile, which is not conducive to mimicking the forgetting function of the brain. Given that the resistance states of memristor emulators are volatile after power down, this paper exhibits a scalable neuristor built with a half-wave memristor emulator. The proposed neuristor demonstrates four critical features for action-potential-based computing: the all-or-nothing spiking of an action potential, threshold-driven spiking, diverse periodic spiking and symmetric anti-Hebbian learning rule of spike-timing-dependent plasticity. Particularly, there are no complex shape and duration constraints on pre- and post-spikes for implementing the symmetric anti-Hebbian learning rule.

This paper proposes a novel jerk circuit obtained by using an alternative nonlinear bipole component of inductor and diode in parallel. The circuit is described by five differential equations and investigated by the stability analysis, equilibria points, Kaplan–Yorke dimension, phase portraits, Lyapunov characteristic exponent estimation, bifurcation diagram and the 0–1 test chaos detection. The control parameter is adopted by varying the inductor $L$ value, this system can display periodic orbit, quasi-periodic orbit and chaotic behavior. The dynamic influence of transit diode capacitance is done and this confirms the robustness of the system to noise influence. The validity of the numerical simulations is experimentally realized through the phase portraits of the circuit. Finally, the synchronization of the systems is studied and time simulation results are presented.