Journal of Circuits, Systems and Computers

With the aggressive scaling of the transistor, Negative Bias Temperature Instability (NBTI) has become the most dominant aging effect which causes the device parameter to degrade over its lifetime. This device parameter degradation of logic gates in nanometer technology is a major concern for the reliability of the digital circuit. It becomes even more critical when it comes to power gating structure, as small NBTI effect on PMOS sleep transistor used in header-based power gating structure would seriously affect the reliability, performance of the whole logic circuit. The conventional method of mitigating the NBTI effect is to oversize the sleep transistor, but it also gives rise to leakage overhead. In this work, a novel NBTI aware power gating architecture is presented to improve the lifetime of the circuit. Here, sleep transistors (STs) are switched ON/OFF periodically and a greater number of STs are turned ON, when NBTI related degradation reaches to its threshold value so that STs get more time to anneal NBTI degradation and improve its lifetime. Simulation result on ISCAS’85 benchmark circuits shows for 40% sleep signal, an average of 51.2% and 14% lifetime improvement with respect to the conventional over-sizing (OS) technique and normal stress probability control method, respectively with some power and area overhead.

The revolution in the Internet of Things (IoT) is redesigning and reshaping the healthcare system technologically, economically and socially. The emerging and rapidly growing IoT-based Smart Healthcare System (SHCS) is seen as a sustainable solution to reduce the burden on the existing healthcare system due to increasing diseases and limited medical infrastructure. IoT-based SHCS plays a vital role in delivery of healthcare services in rural and remote areas where the essential medical amenities, necessary infrastructures and qualified medical practitioners are not available. Therefore, in this paper, a comprehensive investigation of futuristic IoT-based SHCS and its constituents is presented. This paper provides exhaustive review on different techniques and technologies dealing with smart healthcare framework, physiological sensing, signal processing, data communication, cloud computing and data analytics used in IoT-based SHCS. A comparative analysis of existing literature has been carried out to identify the recent trends and advancements in this very dynamic field of global importance. In addition to this, it highlights different issues and challenges, along with the recommendation for further research in the field. The prime objective of this paper is to deliver the state-of-the-art understanding and update about IoT-based SHCS and its constituents by providing a good source of information to the researchers, service providers, technologists, medical practitioners and the general population.

Physical Unclonable Functions (PUFs) are considered to be a promising technology that provides a hardware root-of-trust for integrated circuit (IC) applications. PUFs exploit the intrinsic process variations that map a set of challenges to a set of responses. The intrinsic process variations are caused by uncontrollable deviations in the IC manufacturing process, which are unique and random from die to die and wafer to wafer. As the PUF output is device-specific, PUFs can, therefore, be used in IC identification and authentication, and cryptographic key generation. Nevertheless, many different successful attack techniques have already revealed vulnerabilities in certain PUFs, including invasive, semi-invasive and noninvasive attacks. In this work, we survey some of the known attacks on PUFs. We also survey the countermeasures to these types of attack presented in recent literature, and finally, discuss the future challenges. Through this survey, the susceptibility of PUFs to attacks is highlighted and this information may be used to improve the quality of future PUF-based application designs.

The need of energy-efficient, high-speed, and low-offset analog-to-digital converters is forcing to design the dynamic latch comparators to enhance the speed and energy efficiency with minimum offset. This paper presents a novel double tail dynamic latch comparator using bulk-driven process and common-gate (CG) amplifier in amplification stage. The gain of amplification stage is enhanced using GACOBA load in which gain is controlled by bulk amplification through CG amplifier. It results in remarkable enhancement in regeneration speed and reduction in power consumption. The analytical expressions of delay and offset due to mismatch are also derived. These derivations explore the key contributors to reduce the delay and offset of proposed comparator. The outcomes are verified in CADENCE SPECTRE at 45-nm CMOS process technology through various simulations and Monte-Carlo analysis at different process corners. The post-layout analysis validates the simulation results. The proposed comparator is 93% more energy-efficient and lessens more than 84% delay in comparison of conventional design. The 1–$\sigma$ input offset voltage and average input voltage error due to kickback noise are 2.48mV and 0.824$\mu$V, respectively at 0.8V power supply with 34.32$\mu$m² active area.

In this paper, a complex second-order charge-sampling switched $g_m$-$C$ semi-passive band-pass filter (BPF) is presented which by using the technique of increasing the number of input signal phases without the need to increase the number of clock phases and switches, has been improved out-of-band rejection, near-band rejection and the quality factor of the filter. In addition to the tunable bandwidth and center frequency that can be tuned independently, the proposed filter provides a very high linearity and consumes low power. Designed and simulated in a $0.18\text{-}\mu$m standard CMOS technology, this filter operating at 1GS/s sampling rate has an adjustable center frequency of 11.68–28.5MHz and a tunable bandwidth of 1.8–8.74MHz. Also, the out-of-band rejection varies from 37dB to 39dB in an offset frequency of 3 fc. The in-band IIP3, power consumption and input-referred noise are 28dBm, 5mW and 13.8–18.8nv/sqrt (Hz), respectively

Convolutional neural network (CNN) is one of the most promising algorithms that outweighs other traditional methods in terms of accuracy in classification tasks. However, several CNNs, such as VGG, demand a huge computation in convolutional layers. Many accelerators implemented on powerful FPGAs have been introduced to address the problems. In this paper, we present a VGG-based accelerator which is optimized for a low-cost FPGA. In order to optimize the FPGA resource of logic element and memory, we propose a dedicated input buffer that maximizes the data reuse. In addition, we design a low resource processing engine with the optimal number of Multiply Accumulate (MAC) units. In the experiments, we use VGG16 model for inference to evaluate the performance of our accelerator and achieve a throughput of 38.8GOPS at a clock speed of 150MHz on Intel Cyclone V SX SoC. The experimental results show that our design is better than previous works in terms of resource efficiency.

This paper introduces four new resistorless, third-order, electronically tunable, quadrature sinusoidal oscillators using three operational transconductance amplifiers (OTAs) and three capacitors. The proposed third-order quadrature sinusoidal oscillators (TOQSOs) provide noninteracting control of the oscillation condition (OC) and oscillation frequency (OF) by changing the transconductance of different OTAs, to produce sustained oscillations and offer quadrature output voltages and currents. Two of the proposed quadrature oscillator circuits have capacitor control of OF, a feature, useful in capacitive transducers. The presented TOQSO structures have good frequency stability and exhibit low active and passive sensitivities. PSPICE simulations using CMOS OTAs along with hardware results (using off-the-shelf available OTA IC LM13700) have also been provided to confirm the workability of the presented circuits.

Increased utilization of nonlinear loads in the power distribution system with profound integration of renewable energy requires improved power quality control. This paper proposes a Reformed Second Order Generalized Integrated (R-SOGI) control scheme for enhancing the output of the Dynamic Voltage Restorer (DVR) for the objective of achieving the desired sinusoidal voltage wave shape at the common point of services and harmonic reduction. The DVR incorporates a Solar Photovoltaic (SPV) system using the Z-source Inverter (ZSI), providing the necessary active power to mitigate the voltage sag/swell and power demand. ZSI offers step-down as well as step-up abilities, it makes the converters to operate in the conditions of shoot-through. Therefore, the application of ZSI-based DVR topology seems very promising. The compensating reference voltage is generated by the R-SOGI algorithm, which offers superior output under conditions for grid voltage irregularities, including voltage sag/swell and unbalanced and distorted utility grid voltages. In comparison to DVR based on the VSI voltage inverter (VSI), the response from ZSI-DVR to a reduction of voltage distortions and harmonics is investigated. An experimental SPV ZSI-DVR prototype is developed in the laboratory to check the effectiveness of the controller and is tested under balanced and unbalanced supply and dynamic load conditions.

Coherent Signal-Subspace (CSS) is a technique to separate the wide frequency band into narrowband components which can be applied in many applications such as smart antennas for wireless communications and radar. However, CSS is computationally intensive and may not achieve the real-time requirement. Therefore, this work aims to propose an efficient implementation of the CSS method on Field-Programmable Gate Array (FPGA) to achieve the desired performance. Different parallelization and optimization techniques such as loop unrolling, loop pipelining, dataflow, and loop flattening are adopted and applied to explore the opportunities of any computation and storage that could be eliminated in order to achieve high efficiency. The results of the proposed optimized implementation achieve the highest performance compared with other related implementations.

In this paper, 11-level multilevel inverter with reduced power switch configuration is developed and investigated. This proposed configuration can be extended for $N$ levels with the required number of power switches. Comparative analysis between the proposed multilevel inverter topology and well-known existing multilevel inverter topologies is carried out. Fundamental switching angle calculation for the power switches of the proposed topology has been optimized using black widow optimization algorithm technique and also the proposed topology has been tested with the classical multicarrier alternative phase opposition disposition PWM technique. To test the effectiveness of the proposed topology, different tests have been conducted such as testing with different modulation indexes, DC input voltages, load settings and voltage ride-through capabilities. This paper presents various simulation and experimental results under various operating conditions to prove the performance of the proposed multilevel inverter topology.

In this paper, an RF front-end (RFFE) circuit consisting of a low noise amplifier (LNA) and a down-conversion mixer for vehicle-to-everything (V2X) applications in a 65-nm CMOS process is presented. V2X standard has a carrier frequency of 5.9GHz with 10 and 20MHz bandwidth options. The LNA topology of the RFFE is based on an inductively degenerated cascode common source differential approach. The mixer design uses a double-balanced topology with a charge injection method to enhance the linearity and noise figure performance. The RFFE design shows a single sideband integrated noise figure of 4.47dB with a total conversion gain of 28dB. The IIP3 is obtained as $-$17dBm with charge injection in the mixer which is an improvement of 5dB as compared to no charge injection. The design consumes a total current of 10.24mA from a 1.2-V supply. This work is the first CMOS RFFE design implemented for V2X applications.

Prolonging the lifetime of wireless sensor networks (WSN) is the biggest challenging issue. In wireless multimedia sensor networks (WMSNs), sensor nodes have limited energy resource and to increase the lifetime of the network, it is necessary to design an effective fast algorithm that aims at reducing the consumed power. This paper proposes an energy-efficient discrete cosine transform (DCT) approximation requiring only 12 additions. Associated with a JPEG compression chain, this DCT approximation ensures a very good rate-distortion compromise, but above all, a very low computational complexity and significant compatibility with the exact DCT. Simulation results clearly show that the proposed fast transform algorithm achieves a better trade-off between image quality, computational complexity and energy consumption compared to any existing pruned DCT approximations. Furthermore, it is very suitable for the resource constrained wireless visual sensor networks (WVSNs) requiring low bitrates.

Considering attitude-only measurements, physical limitations of actuator and state-independent observer time, a distributed velocity-free attitude coordination control problem for multiple formation spacecraft with torque saturation is studied in this work. Initially, aiming at speeding up the convergence rate and realizing the maximum value of the convergence time without requiring prior knowledge of the initial system state values, a fixed-time observer is constructed to estimate the desired time-varying states in fixed time. Then, a filter system is developed for the spacecraft with attitude-only measurements. With the application of the fixed-time observers and the filter systems, a distributed velocity-free attitude coordination controller with torque constraint is designed to grantee that the leader with desired state trajectory can be tracked coordinately by the formation spacecraft. Finally, the performance of the proposed controller is demonstrated by simulation results.

Overhead catenary system (OCS) images exhibit great variations with clutter backgrounds, complex scenes and oblique views which pose great difficulty for automatic pillar number plate (NP) detection and recognition (NPDAR). Although these tasks have an important and practical significance for railway transportation, little researches have been done on these fields. In this paper, we propose a complete automatic NPDAR system with two main advantages: (1) For detection task, we propose Skip Connection Attention Module (SCAM) for adaptive feature refinement. Based on SCAM, the Attention_Guided Feature Fusion (AFF) module is designed for building high-level feature maps at different scales. (2) A novel convolution module, width/height convolution module (W/H-CM) was designed for NP recognition to capture global feature information efficiently. The W/H-CM extracts contextual information from two other perspectives compared to common convolution operation and iteratively generates supplementary information, making the representation of features more comprehensive. Both of them can incorporate with state-of-art feed forward network architecture in an end-to-end training fashion. We conduct extensive experiments on both our datasets and standard benchmarks PASCAL-VOC, MS COCO to verify competitive performance of our method.

Due to the complication control structure and heavy burden in computation of the Permanent Magnet Synchronous Motor (PMSM) control strategy, a new cascade control strategy is proposed, which is combined with advanced control algorithm of Active Disturbance Rejection Control (ADRC), Finite Control Set Model Predictive Control (FCS-MPC) and Kalman filtering. ADRC is designed in detail for speed control, in order to reduce the burden of Extended State Observer (ESO) in ADRC, a Kalman filter is designed to simultaneously observe load disturbance and back Electromotive Force (EMF), which can also reduce influence of the noise. While the estimated EMF is used for the current loop FCS-MPC control, it is improved with a method of best vector selection and duty cycle optimization. The proposed combined control scheme is verified in MATLAB simulation environment, through detailed analysis, it shows both good performance in steady state and dynamic response.

The quantum-dot cellular automata technology has great attention in nanoscale digital circuits design due to its high-speed and high-dense. Shift registers play vital role in digital circuits design. So, efficient implementation of shift register circuits in this technology is in the focal point of researches in digital circuits design. In this study, new structures are proposed for the shift register circuits in single layer, three layers and five layers based on inherent quantum-dot cellular automata clock. The QCADesigner tool version 2.0.3 is employed for simulation and verification of functionality of the proposed structures for the serial-input-serial-output shift register circuits. The results demonstrate that the developed 3-bit, 4-bit and 5-bit coplanar shift register circuits require 32, 44 and 56 cells, respectively. The comparison results demonstrate that the developed circuits provide advantages compared to other circuits in terms of area, cell count, clock cycles and cost.

This paper proposes a well-optimized FPGA implementation of a chaos-based cryptosystem for real-time image encryption and decryption. A highly sensitive Pseudo-Random Number Generator (PRNG) based on the Lorenz chaotic system is designed to generate pseudo-random numbers. A high-quality encryption key is acquired by encrypting the numbers of a 128-bit counter using the PRNG. For image encryption, the image is first decomposed into 128-bit blocks. Then, the blocks are encrypted by XORing pixels with the key stream. $R$ cycles of encryption can be achieved to increase complexity. Finally, the blocks are concatenated to form an encrypted image. The algorithm is designed, implemented, and validated on the Xilinx Zynq FPGA platform using the Vivado/System Generator tool. The hardware design is well optimized for pipeline processing and low resource utilization. The experimental synthesis indicates that the provided architecture achieves high performance in terms of frequency and throughput. The encryption scheme is evaluated and analyzed by several tools and tests using different images. The experimental simulation results demonstrate that the hardware implementation is faster than a software implementation while maintaining the technique’s effectiveness. The proposed hardware implementation is extremely adopted for secret image encryption and decryption that can be used in real-time applications.

The welding robot system designed in this paper is helpful to realize welding automation. The closed loop control system and algorithm of arc rotating speed have been designed, so arc rotating speed was stabilized near the set value and the tracking accuracy of fillet weld has been improved by the rotating arc sensor. A data acquisition system and a motion control system have been designed based on multi-sensor technology. The mapping relationship between the features in the welding seam image and the pose of the welding gun was established, so as to realize the identification of the pose of the welding gun based on three-wire laser vision sensing technology. The effect of wire extension, welding currents and welding voltages on the current waveform was investigated based on the rotating arc sensor. By using the designed system and algorithm, the welding deviations recognition experiment, the arc rotating speed control experiment and the tracking experiment of the right-angle welding seam have been carried out. The experimental results showed that the welding deviations were located within $\pm 1$mm, and the welding robot can track the complex welding seam accurately and reliably.

The Vehicular Ad hoc NETworks (VANETs) are of high mobile and dynamic in nature. They are highly prone to network discontinuity, thereby the applications running on the vehicles get degraded in its service. The network selection for VANETs is done based on network attributes and user Quality of Service (QoS) demands. In this work, a two-phase access network selection scheme is proposed for VANETs. In the first phase, the available networks are ranked based on QoS demands using Weighted Sum Method (WSM). During the second phase, based on availability of resources, handoff decision and access network selection are carried out using game theory approach. Here, the vehicle and network play the game by adopting different strategies, thereby the optimum Nash Equilibrium (NE) is obtained. The simulation results validate that the proposed scheme outperforms the conventional Multiple Attribute Decision Making (MADM) schemes.

In this paper, the design of nearly linear-phase recursive digital filters using a constrained optimization method is investigated. The method is based on existing constrained optimization techniques for nearly linear-phase IIR digital filters, and it is expected to be useful in applications where both magnitude and phase response specifications are required to be satisfied. Starting from an initial filter, the proposed method minimizes the group delay deviation under a set of linear constraints in terms of the magnitude response and filter stability. Improved sampling functions are introduced to the optimization problem, which are used to control the sampling points that are used for approximating the group delay and the rest of the constraints in various frequency bands. By using the proposed sampling functions we get an improved IIR filter response.