Journal of Circuits, Systems and Computers

In this paper, a new grounded inductor simulator employing two current feedback operational amplifiers (CFOAs), three resistors and one grounded capacitor which is suitable for IC fabrication is proposed. Also, a new voltage-mode (VM) universal filter with three input and single output is given as application example of the grounded inductor simulator. The universal filter with low output impedance can be easily cascaded with other VM circuits. Both of the proposed circuits have the feature of improved low frequency performances, and can be easily constructed by two commercially available active devices such as AD844s. However, both inductor simulator and universal filter need a single passive component matching condition. Simulation and experimental test results are given to demonstrate the performance and workability of the proposed grounded inductor simulator and filter structure.

Binary and ternary adders are frequently used to speed-up many digital signal processing (DSP) operations like multiplication, compression, filtering, convolution, etc. FPGA realization of these circuits uses a combination of look-up tables (LUTs) and carry-chains. Alternatively, inbuilt operators and parameterizable IP cores provide an efficient means of implementing these circuits. However, the realization is not optimal in the sense that the full potential of the underlying resources is not utilized. In this paper, we use technology-dependent approaches to restructure the Boolean networks corresponding to these circuits. The restructured networks are then mapped optimally onto the FPGA fabric using minimum possible resources. Our analysis shows a subsequent speed-up in the performance of these circuits when compared to different conventional and existing approaches.

The Discrete Cosine Transform (DCT) structure plays a significant role in the signal processing applications such as image and video processing applications. In the traditional hardware design, the 8-point DCT architecture contains more number of logical slices in it. Also, it consists of number of multipliers to update the weight. This leads to huge area consumption and power dissipation in that architecture. To mitigate the conventional drawbacks, this paper presents a novel Hierarchical-based Expression (HBE)-Multiple Constant Multiplication (MCM)-based multiplier architecture design for the 8-point DCT structure used in the video CODEC applications. The proposed work involves modified data path architecture and Floating Point Processing Element (FPPE) architecture. Our proposed design of the multipliers and DCT architecture requires minimum number of components when compared to the traditional DCT method. The HBE-MCM-based multiplier architecture includes shifters and adders. The number of Flip-Flops (FFs) and Look Up Tables (LUTs) used in the proposed architecture is reduced. The power consumption is reduced due to the reduction in the size of the components. This design is synthesized in VERILOG code language and implemented in the Field Programmable Gate Array (FPGA). The performance of the proposed architecture is evaluated by comparing it with traditional DCT architecture in terms of the Number of FFs, Number of LUTs, area, power, delay and speed.

This paper describes the design of a novel cascode-grounded tunable active inductor and its application in an active band-pass filter (BPF) suitable for multi-band radio frequency (RF) front-end circuits. The proposed active inductor circuit uses feedback resistance to improve the equivalent inductance and the quality factor. The novelty of this work lies on the use of a few number of multi-finger transistors, which allows reducing strongly the power consumption and the silicon area. In other words, we demonstrate that the use of variable P-type Metal-Oxide-Semiconductor (PMOS) resistor and controllable current source have a good potential for wide tuning in terms of inductance value, quality factor and frequency operation. The RF BPF is realized using the proposed active inductor with suitable input and output buffer stages. The tuning of the center frequency for multi-band operation is achieved through control voltages. The designed active inductor and RF BPF have been implemented in a standard 0.13$\mu$m Complementary Metal Oxide Semiconductor (CMOS) technology. The simulation results are compared between schematic and post-layout design for inductance value, quality factor, transmission coefficient S21 and noise. This design yields encouraging results: the inductance value can be tuned from 10.94 to 44.17nH with an optimal quality factor around 2,581. In addition, the center frequency of the BPF can be tuned between 2 and 4.84GHz with an average insertion loss of $10.92\pm 0.31$dB. Throughout this range, the noise figure is between 10.49 and 9.22dB with an input referred 1dB compression point of $-0.25$dBm and IIP3 of 7.36dBm. The filter occupies 25.43$\mu \mathrm{\text{m}}\times 21.56\mu$m of active area without pads and consumes between 2.38 and 2.84mW from a 1V supplying voltage.

In recent years, due to the growing population of the elderly, falls of elderly people have aroused wide public concern. Detecting timely falls of the elderly is significant to their safety. Numerous challenges exist in real-time fall detection systems because some features of normal human activities are greatly similar to the characteristics of falls. To address these problems, we propose a novel fall detection scheme and build a health-care system to detect falls of the elderly based on a real-time video surveillance system and a smart phone. The system contains two major modules. The first module is a feature extraction module. We adopt the Gaussian mixture model, tracking learning detecting algorithm and logpolar histogram to extract the characteristics of falls from the video surveillance system and the sensors embedded in mobile phones. The main purpose of the second module is to detect a fall-based on the features obtained in the first module. The experimental results show that every module is significant. Besides, our system is effective to separate falls from other similar actions such as bend down with an accuracy rate of more than 98% and performs better than other state-of-the-art fall detection systems.

Energy technologies and their efficient use plays a vital role in socio-economic development of any country. In the recent years, the restructuring of electricity market evolves some major improvements in the technologies of energy production and thus, it has paved the way for increasing the applications of Distributed Generation (DG) with renewable energy sources. In this research, the optimal placement and sizing of multiple DGs are achieved by a novel indicator United Bus and Line Voltage Firmness Factor (UBL_VFF). The objectives of this work are the minimization of system losses and maximization of voltage stability and they are achieved by identifying the weakest voltage bus due to the weakest link in the system. Particle Swarm Optimization (PSO) is used for solving this optimization problem. The effectiveness of this proposed approach is tested in 33 and 69 bus radial distribution test systems. The results of this proposed method is compared with the results reported in the contemporary literature. The results have proved to be robust in terms of reduction in system losses and maximization of bus and line voltage stability.

These days, computer-based image registration techniques are increasingly being used in the area of medical imaging as they offer significant benefits for aligning different images together and for visualizing their combined images. However, these techniques require an enormous amount of computation time due to the high resolution and complex nature of the medical images. We propose to alleviate this problem by using a dedicated Network-on-Chip (NoC)-based hardware platform for image registration. This paper describes a novel technique for field-programmable gate array (FPGA) implementation of the B-Spline-based free form deformation (FFD) algorithm, i.e., a widely used algorithm for modeling geometric shapes in a computerized environment. For performance enhancement, we have utilized a lightweight circuit-switched NoC architecture, which is adaptable to most FPGAs. The design description is captured in the Verilog language and implemented using the Xilinx XC2v6000 device at 37MHz. The proposed design is parameterizable at the compile time and supports a wide range of the image resolutions and computational precisions. The experimental results have shown a significant improvement in performance when compared with the other existing hardware implementations of the B-spline-based FFD algorithm.

Three-dimensional (3D) integration provides many benefits including high density, high bandwidth and low power consumption. Through-silicon via (TSV), which provides communication links for dies in vertical direction, is a critical design issue in 3D integration. Nevertheless, TSV is susceptible to failure in the fabrication and bonding, which may lead to partial interconnection in vertical direction, and thus can severely increase the cost and decrease the yield. To solve this issue, this paper proposes a TSV fault-tolerant scheme based on failure classification. Specifically, a 32-bit TSV channel is divided into four groups. Based on the results of TSV testing, inter-group TSV serialization, intra-group TSV serialization and localized fault-tolerant routing are proposed to solve different TSV failure classifications. By comparing with the existing works, the experiment results show the superiority of the proposed method in improving the overall network performance with an acceptable area and power overhead.

In natural language processing (NLP), a crucial subsystem in a wide range of applications is a part-of-speech (POS) tagger, which labels (or classifies) unannotated words of natural language with POS labels corresponding to categories such as noun, verb or adjective. This paper proposes a model of uniform-design genetic expression programming (UGEP) for POS tagging. UGEP is used to search for appropriate structures in function space of POS tagging problems. After the evolution of sequence of tags, GEP can find the best individual as solution. Experiments on Brown Corpus show that (1) in closed lexicon tests, UGEP model can get higher accuracy rate of 98.8% which is much better than genetic algorithm model, neural networks and hidden Markov model (HMM) model.; (2) in open lexicon tests, the proposed model can also achieve higher accuracy rate of 97.4% and a high accuracy rate on unknown words of 88.6%.

The objective of the work is to predict heart disease using computing techniques like an oppositional firefly with BAT and rule-based fuzzy logic (RBFL). The system would help the doctors to automate heart disease diagnosis and to enhance the medical care. In this paper, a hybrid OFBAT-RBFL heart disease diagnosis system is designed. Here, at first, the relevant features are selected from the dataset using locality preserving projection (LPP) algorithm which helps the diagnosis system to develop a classification model using the fuzzy logic system. After that, the rules for the fuzzy system are created from the sample data. Among the entire rules, the important and relevant group of rules are selected using OFBAT algorithm. Here, the opposition based learning (OBL) is hybrid to the firefly with BAT algorithm to improve the performance of the FAT algorithm while optimizing the rules of the fuzzy logic system. Next, the fuzzy system is designed with the help of designed fuzzy rules and membership functions so that classification can be carried out within the fuzzy system designed. At last, the experimentation is performed by means of publicly available UCI datasets, i.e., Cleveland, Hungarian and Switzerland datasets. The experimentation result proves that the RBFL prediction algorithm outperformed the existing approach by attaining the accuracy of 78%.

This paper presents a system-level design procedure for wireless receivers, which allows an optimum distribution of the specifications-per-stage along the receiver. The main idea hereby developed is to start from a specific set of requirements (given by the selected telecommunications standards) in terms of bit-error-rate (BER) and blocker mask scenario in frequency domain, and to finally achieve a certain set of specifications for each stage in the receiver chain (i.e., LNA, mixer, baseband and ADC). The proposed system-level design algorithm allows fixing the receiver specifications-per-stage with a reduced set of equations and successive iterations. Moreover, an optimum design for baseband section (i.e., complex filter and the ADC) is also found, by achieving an optimum trade-off between filter order and ADC equivalent-number-of-bits (ENOB). In order to validate the hereby proposed algorithm, a low-energy Bluetooth low-IF receiver has been modeled and simulated (by Simulink), and extensive time-domain simulation results have been provided, complying with the expected Bluetooth standard signal-to-noise-and-distortion ratio (SNDR).

A novel near-threshold voltage startup monolithic boost converter is presented in this paper using an adaptive sleeping time control (ASTC) scheme for low-power applications. The proposed ASTC scheme can promote the power efficiency of the current-mode boost converter under light load by automatically adjusting the sleep time of the converter, and the converter's quiescent current drops down to 4$\mu$A during the sleeping period. In addition, a new soft-start method is introduced to make the boost converter start up with a near-threshold input voltage. The proposed boost converter was fabricated in a standard 0.18$\mu$m CMOS process and occupies a small chip area of 0.50$\mathrm{\text{mm}}\times 1.22$mm. Experimental results show that the boost converter achieves the minimum 0.5-V startup voltage when the output voltage is set to 1.8V. After startup, the input voltage range can be expanded from 0.3V to 1.5V with a switching frequency of 1MHz. In addition, a peak efficiency of 94% and a minimum efficiency of 81% are measured at the 1.5-V input voltage as the load current ranges from 0.1mA to 100mA.

Boolean Satisfiability (SAT)-based channel routing with via-aware pin doglegging is presented in this paper. The effect of the pin dogleg layout of connecting wires has been tested separately for input–output pins and output pins only with controlled use of vias for dogleg during detailed routing. Dogleg may reduce the channel width required for laying down all nets and hence decrease the total chip area. However, invalid selection of dogleg may increase the channel width or may identify a routable circuit as unroutable. Unwanted dogleg may also increase the use of vias (switches) required for changing the track from one to another and may create a congested area with vias. Congested via may introduce lithographic printing problem during manufacturing and power leakage problem. The proposed technique considers all these constraints to provide an optimal result and gives a compact layout for a circuit with controlled via for doglegging. The results obtained show that pin dogleg layout produces a more compact layout for connecting wires with supervised via when compared to dogleg-free routing or doglegged routing with unsupervised via for some standard benchmark circuits. It yields optimal results with reduced number of tracks in a channel and smaller chip size.

Rational approximations for fractional order systems are discussed in this paper. A fix-pole method is derived whereby a fractional order system is efficiently approximated by a low order integer system via simple algebraic algorithms. An adjacent congruent triangle (ACT) criterion is presented to analyze our method and compare it with existing results in a unified framework. The proposed fix-pole method has a trade-off that sacrifices partly the fitting error in exchange for simple approximations of complicated fractional order systems. The quality of the fix-pole approximations can be improved to be acceptable in practical or numerical implementations by narrowing the fitting frequency band. Finally, numerical examples illustrate the effectiveness of our methods.

One of the most essential operations in biological sequence analysis is multiple sequence alignment (MSA), where it is used for constructing evolutionary trees for DNA sequences and for analyzing the protein structures to help design new proteins. In this research study, a new method for solving sequence alignment problem is proposed, which is named improved tabu search (ITS). This algorithm is based on the classical tabu search (TS) optimizing technique. ITS is implemented in order to obtain results of multiple sequence alignment. Several variants concerning neighborhood generation and intensification/diversification strategies for our proposed ITS are investigated. Simulation results on a large scale of datasets have shown the efficacy of the developed approach and its capacity to achieve good quality solutions in terms of scores comparing to those given by other existing methods.

This paper presents a new tail current-shaping technique to improve the phase noise of an LC quadrature VCO (LC-QVCO) based on Gaussian pulse generator (GPG). The GPG makes a narrow pulse from oscillator sinusoidal output and injects it back to gates of tail transistors to reduce the root-mean-square (RMS) value of impulse sensitivity function (ISF) and to improve phase noise. It will be shown that by utilizing a GPG, total phase noise improvement will be as high as 6dB. The proposed circuit was designed and simulated by ADS simulator using 0.18$\mu$m TSMC RF CMOS design kit. The phase noise's at 3MHz frequency offset and carrier frequencies of 2.43GHz and 2.6GHz are –141dBc/Hz and –135dBc/Hz, respectively, while the total power consumption is 14mW under 1.8V supply voltage. Tuning range is from 2.43GHz to 2.6GHz. The figure of merit (FOM) values for the proposed LC-QVCO at 3MHz frequency offset are –187.6dBc/Hz and –182.3dBc/Hz for 2.43GHz and 2.6GHz carrier frequencies, respectively.

A low-cost multi-edged rectangular microstrip fractal antenna (RMFA) yielding a huge bandwidth of 8.62GHz has been proposed in this paper. The proposed fractal antenna design constitutes a radiation patch, fed with 50$\mathrm{\Omega }$ microstrip line and a partial ground plane. The partial ground plane is the combination of shapes of rectangle and three-point arc. The proposed antenna is simulated as well as fabricated. The simulated results using electromagnetic solver software and measured with vector network analyzer bench MS46322A are presented and compared. The various parameters such as return loss, voltage standing wave ratio (VSWR), antenna impedance, gain, directivity, group delay and phase of $S_{21}$, radiation efficiency and patterns are presented here. The depth of return loss is improved for a wide range of frequencies. The proposed fractal antenna is further extended to linear array to improve the gain and impedance bandwidth. The simulated and measured results prove the superiority of the proposed antenna.

This paper presents a design exploration, at both system and circuit levels, of integrated transceivers for the upcoming fifth generation (5G) of wireless communications. First, a system level model for 5G communications is carried out to derive transceiver design specifications. Being 5G still in pre-standardization phase, a few currently used standards (ECMA-387, IEEE 802.15.3c, and LTE-A) are taken into account as the reference for the signal format. Following a top-down flow, this work presents the design in 65nm CMOS SOI and bulk technologies of the key blocks of a fully integrated transceiver: low noise amplifier (LNA), power amplifier (PA) and on-chip antenna. Different circuit topologies are presented and compared allowing for different trade-offs between gain, power consumption, noise figure, output power, linearity, integration cost and link performance. The best configuration of antenna and LNA co-design results in a peak gain higher than 27dB, a noise figure below 5dB and a power consumption of 35mW. A linear PA design is presented to face the high Peak to Average Power Ratio (PAPR) of multi-carrier transmissions envisaged for 5G, featuring a 1dB compression point output power (OP1dB) of 8.2dBm. The delivered output power in the linear region can be increased up to 13.2dBm by combining four basic PA blocks through a Wilkinson power combiner/divider circuit. The proposed circuits are shown to enable future 5G connections, operating in a mm-wave spectrum range (spanning 9GHz, from 57GHz to 66GHz), with a data-rate of several Gb/s in a short-range scenario, spanning from few centimeters to tens of meters.