Journal of Circuits, Systems and Computers

In this paper, a new approach based on the real frequency technique (RFT) has been proposed to solve broadband matching problems using cascaded unequal length transmission lines. At the end of the design process, optimum characteristic impedance and delay values of transmission lines are obtained. Two examples are given to illustrate the utilization of the proposed approach.

In road networks, $k$-range nearest neighbor ($k$-RNN) queries locate the $k$-closest neighbors for every point on the road segments, within a given query region defined by the user, based on the network distance. This is an important task because the user's location information may be inaccurate; furthermore, users may be unwilling to reveal their exact location for privacy reasons. Therefore, under this type of specific situation, the server returns candidate objects for every point on the road segments and the client evaluates and chooses exact $k$ nearest objects from the candidate objects. Evaluating the query results at each timestamp to keep the freshness of the query answer, while the query object is moving, will create significant computation burden for the client. We therefore propose an efficient approach called a safe-region-based approach (SRA) for computing a safe segment region and the safe exit points of a moving nearest neighbor (NN) query in a road network. SRA avoids evaluation of candidate answers returned by the location-based server since it will have high computation cost in the query side. Additionally, we applied SRA for a directed road network, where each road network has a particular orientation and the network distances are not symmetric. Our experimental results demonstrate that SRA significantly outperforms a conventional solution in terms of both computational and communication costs.

Recently, storage as a service of cloud computing becomes a new trend to access or share files. Once files are stored in cloud, owner can access files seamlessly by personal computer or mobile device. However, owner may worry about confidentiality and integrity of owner's files stored in cloud because cloud service providers are not always trustworthy. Therefore, there are many kinds of data correctness verification methods proposed to prevent cloud service providers from cheating data owners. Among these models for auditing, bilinear pairing can achieve the most efficient way to verify data correctness and batch auditing. Although auditing methods can ensure whether data is stored properly, it is not considered that the data may be a secret data or a data owner does not want to be known by both auditors and cloud service providers. Another important issue is providing dynamic data of auditing in cloud. Wang et al.¹³ proposed a scheme that can provide public auditing and dynamic data, but it still cannot guarantee whether cloud has updated data honestly. For this reason, we propose a dynamic data guarantee and data confidentiality scheme for public auditing in cloud storage service.

Time-based Analog-to-Digital Converter (TADC), plays a major role in designing Software-Defined Radio (SDR) receivers, at scaled CMOS technologies, as it manifests lower area and power than conventional ADCs. TADC consists of 2 major blocks. The input voltage is converted into a pulse delay using a Voltage-to-Time Converter (VTC). In additions, the pulse delay is converted into a digital word using a Time-to-Digital Converter (TDC). In this paper, a novel fully-differential VTC based on a new methodology is presented which reports a highly-linear design. A metal-insulator-metal (MIM) capacitor as well as a dynamic calibration technique based on a set of large-sized capacitor-based voltage dividers circuits are utilized to automatically compensate the Process-Voltage-Temperature (PVT) variations. Moreover, the layout design is introduced. The proposed design operates on a 1GS/s sampling frequency with a supply voltage of 1.2V. After calibration, simulation results, using TSMC 65nm CMOS technology, report a 1.42V wider dynamic range due to the differential mechanism with a 3% linearity error. This design achieves a resolution up to 14 bits, a 0.07 fJ/conversion FOM, a 229$\mu$m² area and a 0.25mW power. The simulation results are compared to the single-ended VTC results and the state-of-the-art analog-part ADCs results to show the strength of the proposed design.

In this paper, a comparative study between performance of BJT and CMOS technologies is performed by implementing two novel BJT and CMOS differential voltage current conveyors (DVCCs) with minimum and equivalent sizes. In this study, “size” means the number of the transistors used in a design. The CMOS-DVCC consists of only 12 MOS transistors, and the BJT-DVCC includes 13 BJTs. The implementations are performed in Proteus-7 environment, and the two DVCCs are formulized with their real parameters. The two chips are modeled at low frequency, and it is shown that the CMOS-DVCC has acceptable performance and behavior to operate as a DVCC while the parameters of the BJT-DVCC are far from an ideal DVCC, so the CMOS-DVCC can be used to design electronic devices. The comparative analysis shows to achieve a reliable and acceptable BJT implementation of a DVCC, it is inevitable to increase the size of the BJT implementation. To prove this claim, another novel acceptable BJT-DVCC with larger size is presented and modeled. It is also demonstrated that the acceptable BJT-DVCC is also the first and only DVCC reported in the literature which is applicable to high-power applications, and this is the other contribution of this work.

This paper presents the design of a 60GHz-band LNA intended for the 63.72–65.88GHz frequency range (channel-4 of the 60GHz band). The LNA is designed in a 65-nm CMOS technology and the design methodology is based on a constant-current-density biasing scheme. Prior to designing the LNA, a detailed investigation into the transistor and passives performances at millimeter-wave (MMW) frequencies is carried out. It is shown that biasing the transistors for an optimum noise figure performance does not degrade their power gain significantly. Furthermore, three potential inductive transmission line candidates, based on coplanar waveguide (CPW) and microstrip line (MSL) structures, have been considered to realize the MMW interconnects. Electromagnetic (EM) simulations have been performed to design and compare the performances of these inductive lines. It is shown that the inductive quality factor of a CPW-based inductive transmission line (${\mathrm{\text{Q}}}_{\text{L},\text{C}\text{P}\text{W}})$ is more than 3.4 times higher than its MSL counterpart @ 65GHz. A CPW structure, with an optimized ground-equalizing metal strip density to achieve the highest inductive quality factor, is therefore a preferred choice for the design of MMW interconnects, compared to an MSL. The LNA achieves a measured forward gain of $12\pm 1.44$dB with good input and output impedance matching of better than $-10$dB in the desired frequency range. Covering a chip area of 1256$\mu$m$\times 500\mu$m including the pads, the LNA dissipates a power of only 16.2mW.

This paper aims to design an all-digital phase-locked loop (ADPLL) intended for professional digital audio data conversion applications. The method used for designing is based on an analogy between analog PLL and ADPLL. Managing a low-jitter effect, a comparative study between discrete voltage-controlled oscillator (DVCO) and direct digital synthesis (DDS) based on a pseudorandom binary sequence (PRBS) generator is performed. The features of the design in this work are high-precision and low harmonic distortion DDS which is combined with ADPLL. For model-based design validation, a rapid register transfer level (RTL) with VHSIC hardware description language (VHDL) is practiced and the dynamic performance result indicates a significant improvement in total harmonic distortion (THD) ($\le -130$dB) and a better resolution of 18.97bits for audio applications based on the aid of phase dithering DDS enhancement circuit.

The work proposes an improved technique to design a low power 8-bit asynchronous successive approximation register (ASAR), an analog-to-digital converter (ADC). The proposed ASAR ADC consists of a comparator, ASAR (digital control logic block), and a capacitive-digital-to-analog convertor (C-DAC). The comparator is a preamplier-based improved positive feedback latch circuit which has a built-in sample and hold (S/H) functionality and saves an enormous amount of power. The implemented digital control logic block performing the successive approximation (SA) algorithm is totally unrestrained of the external clock pulse. The outputs from the comparator are given to a XOR logic whose outputs serve as an internally generated clock (ready signal) to trigger the digital control block. Hence, an external clock is not required to initiate the digital control block making its operation asynchronous. By implementing this, the ADC can circumvent the usage of an oversampled clock and can operate on a single low-speed sample clock. This, in turn, saves power and it cuts down the required resilience in sampling rates. The proposed ADC has been designed and simulated using UMC-0.18$\mu$m CMOS technology which dissipates 32.18$\mu$W power when operated on a single 1V power supply and achieves complete 8-bit conversion in 1.09$\mu$s. The relative accuracy of capacitor ratio, aperture jitter and FOM are 0.39$\%$, 1.2ns and 125fJ/conversion-step, respectively.

This paper presents the design of a CMOS low-noise amplifier (LNA) with partial inductive degeneration using active inductors in $0.35\mu$m technology. Both, the inductor of the partial degeneration and the load inductor, are actives. The inductors configurations are cascode with feedback resistance and Wu folded compact. The LNA has a gain of 13.2dB and a noise figure of 4.7dB at 1.8GHz. The layout has an active area of $0.17{\text{mm}}^2$. The results are satisfactory, validating the compact design and demonstrating the technical feasibility of this proposed topology.

In many Multimedia and DSP applications, the fixed-width multipliers are used to avoid infinite growth in the word size. Fixed-width multiplier produces an $n$-bit product with two $n$-bit inputs. This paper presents probabilistic estimation technique applied for the fixed-width radix-8 Booth multiplier for the generation of the compensation bias circuit. The probabilistic estimation circuit for the fixed-width radix-8 Booth multiplier is derived systematically from theoretical computation in preference to time-consuming exhaustive simulations. Results show that the radix-8 direct truncated multiplier reduces the maximum absolute error by 33%, the average error by 22% and the mean square error by 39% for a 12-bit multiplier compared with the radix-4 direct truncated multiplier. Results also demonstrate that, with the probabilistic estimation technique applied to the fixed-width radix-8 Booth multiplier, there is a reduction of 25% in the maximum absolute error, 13.4% reduction in the average error, and 25.13% reduction in the mean square error have been realized compared with the existing fixed-width radix-4 Booth multiplier with probabilistic estimation technique. Standard EDA design tools are used for simulations.

This study presents a two-stage ring voltage-controlled oscillator (VCO) for use in impulse-radio ultra-wideband (IR-UWB) applications. A systematic and efficient graphical optimization method was employed to find the optimal dimensions of the VCO which give a best performance. A good agreement was observed between the desired specifications and simulation results with regard to the optimum component size of the VCO circuit. The operation range of the VCO was extended to cover an ultra-wide tuning range of 176.6%. The phase noise was $-$107.1dBc/Hz at 10MHz offset frequency from a carrier frequency of 4GHz. The power consumption of VCO was 7.41mW from a 1.8V supply voltage. A large tuning range, low power, and appropriate phase noise were obtained with the optimum components size obtained through the optimization method.

The paper presents the idea and implementation of a digital nonlinearity measurement of a voltage ramp. The measurement process is based on evaluation of a time period between the moments when an input voltage ramp and an ideal voltage ramp reach the given value. During this period, the clock pulse train is supplied to the counter. By adjusting the pulse frequency and the circuit parameters, it is possible to obtain the nonlinearity readout in a fraction of percent directly. An automatic range determination has been presented when the reference frequency is constant. Calibration and measurement are completed for two slopes (periods) of the voltage ramp. The measurement error for the proposed method and implementation results were evaluated.

This paper presents a novel inexact full adder based on carbon nanotube field-effect transistors (CNTFET) for approximate computations, which has soared in popularity especially for image processing applications. The proposed design generates the output carry without error. Therefore, the propagation of incorrect value to higher bit positions is avoided. It has the least relative error distance (Relative ED) compared to other approximate full adders reported in the literature. Practical simulations by using MATLAB demonstrate higher peak signal to noise ratio (PSNR) and image quality for motion detector image processing application. HSPICE simulations also confirm the efficiency of the proposed design. Moreover, area occupation is investigated by using electric tool. Power consumption, delay, area and ED are important evaluating factors in this subject. Comparisons are made by a comprehensive parameter (PDAEDP), based on which the new design has 23.8%, 41.5%, 70.5%, 78% and 83.6% higher performance than TGA1, TGA2, AXA1, AXA2 and AXA3, respectively.

This paper presents the analysis, design and implementation of a closed-loop adaptive multistage switched-capacitor converter (AMSCC) for step-down conversion applied to piezoelectric energy harvesting. Its power part consists of two cascaded sub-circuits: (i) Front: a bridge rectifier with a filter capacitor ($C_i$), and (ii) Core: five-stage serial-parallel SC step-down converter with an output capacitor ($C_o$). This rectifier converts piezoelectric AC source into DC type, and $C_i$ captures/stores the energy to build a supply $V_S$, and then the serial-parallel SCC transforms $V_S$ into five different levels as: $V_S$/5, $V_S$/4, $V_S$/3, $V_S$/2, or $V_S$ to charge the battery load. By using the proposed phase generator, a proper level can be manipulated adaptively according to the recent supply and battery voltages for realizing an adaptive multistage charging procedure. Such an adaptive multistage operation is helpful not only to protect the usage of battery, but also to handle the supply variation of piezoelectric device. Some theoretical analysis and design include: formulation, steady-state analysis, stability, capacitance selection, and multistage output response/power. Finally, the performance of AMSCC scheme is simulated and verified experimentally on the implemented prototype circuit, and the results are illustrated to show the efficacy of this scheme.

An energy efficient internal logic approach for designing two 1-bit full adder cells is proposed in this work. It is based on decomposition of the full adder logic into the smaller modules. Low power, high speed and smaller area are the main features of the proposed approach. A modified power aware NAND gate, an essential entity, is also presented. The proposed full adder cells achieve 30.13% and improvement in their power delay product (PDP) metrics when compared with the best reported full adder design. Some of the popular adders and proposed adders are designed with cadence virtuoso tool with UMC 90nm technology operating at 1.2V supply voltage and UMC 55nm CMOS technology operating at 1.0V. These designs are tested on a common environment. During the experiment, it is also found that the proposed adder cells exhibit excellent signal integrity and driving capability when operated at low voltages.

This paper introduces an architecture to enhance coding efficiency (CE) and bandwidth of the delta-sigma modulator (DSM) transmitters. In this architecture a low-pass envelope DSM (LPEDSM) is used instead of the traditional Cartesian low-pass DSM (LPDSM) to reduce the quantization noise and to improve the coding efficiency. The simulation results show that for an uplink long-term evolution (LTE) signal with 1.92MHz bandwidth, 7.8dB peak-to-average power ratio (PAPR), and an oversampling ratio (OSR) of 32, the CE for the polar LPEDSM transmitter is equal to 41.72% in comparison to 9.7% CE for the Cartesian LPDSM transmitter. In the next step, the CE and bandwidth of the transmitter are improved at the same time by using the quantization noise reduction technique in the polar LPEDSM transmitter with parallel baseband. By using this combined technique in the four-branch transmitter baseband part for an uplink LTE signal with 7.68MHz bandwidth, 7.8dB PAPR, and an OSR of 32, the CE is improved from 42.59% to 55.86% with 40dB signal-to-noise-and-distortion ratio (SNDR) while the clock speed is only 61.44MHz which is four times lower than the clock speed requirement of the conventional transmitter baseband part to achieve the same SNDR.

A recently suggested method for evaluating computer performance is applied to real processors. The method is based on notion of Computer Capacity, which is determined only by the computer architecture and can be computed theoretically on the design stage. The computer capacity for different Intel and AMD processors is calculated and the results are compared with those of widely recognized benchmarks. The obtained results show that computer capacity is a reasonable estimate of computer performance.

One of the popular methods of asynchronous logic implementation is based on so called Delay-Insensitive-Minterm-System (DIMS), where a sum-of-minterms (SOM) function is given and each minterm is represented using a state-holding (C-) element. However, such implementation is rather expensive since minterm minimization is not allowed. In the paper, structure called factorized DIMS is proposed. It is shown that under realistic delay limitation, instead of SOM, strong indication can be ensured for the sum of mutually orthogonal product terms resolved into factorized form. It reduces significant implementation complexity.