Journal of Circuits, Systems and Computers

This paper initially presents a modified T–T filter with high $Q$ and derives two nodal admittance matrix (NAM) of the filter. Next, in accordance with the nullor-mirror models of the CCCII, 32 different forms of the Tow–Thomas (T–T) filter using various types of the CCCII are synthesized by bracket notation method. One of the synthesized circuits is analyzed to support the generation method.

Brushless DC motor (BLDCM) is a synchronous motor that contains a permanent magnet on the rotor and armature windings on the stator. It consists of the following characteristics, such as compact form, high efficient, silent operations and low maintenance. The existing BLDCM control systems have some drawbacks such as, it needs higher requirements for control algorithms, it uses more complicated electronics, it holds high noise and the initial rotor movement is not predictable. In order to overcome these issues, a new control mechanism, namely, carrier frequency rate, duty cycle ratio and pulse position range-space vector pulse width modulation (RRR-SVPWM) technique is proposed in this paper to control the speed of BLDCM. Initially, the unregulated AC from the wind turbine system is given to the input of six-legs insulated gate bipolar transistor (IGBT) circuit for converting the unregulated AC to regulated DC. Here, the pulse generator is used to generate the pulses based on certain parameters, such as input three-phase voltage, phase current and DC voltage. Hence, the proposed RRR-SVPWM technique is applied to reduce the noise and maintain a harmonics in a controlled level by placing a high-speed switches in a circuit. Finally, the speed of the BLDCM is increased and controlled by giving an output regulated AC to the motor. The experimental results evaluate the performance of the proposed system in terms of power factor (PF), displacement PF (DPF) and total harmonic distortion (THD).

A new DC/DC converter integrating a full-bridge circuit and a half-bridge pulse-width circuit is studied to realize the advantages of a wide range of zero-voltage switching (ZVS) and less circulating current loss. A half-bridge converter is connected to power switches on the lagging-leg of full-bridge converter to achieve a wider range of ZVS to overcome the disadvantage of narrow ZVS range in conventional full-bridge converter. The output side of half-bridge circuit is linked to the secondary side of the full-bridge converter to decrease the primary circulating current of the full-bridge converter. Therefore, the conduction losses due to the high circulating current in conventional full-bridge converter are reduced. The theoretical analysis is discussed in detail and the effectiveness of the proposed converter is verified by the experimental verifications with a 1440W prototype.

In this paper, we study the problem of reducing the energy consumption for hard real-time systems scheduled according to either fixed-priority (FP) or earliest-deadline-first (EDF) scheme. To balance the static and dynamic energy consumptions, the concept of critical speed was proposed in previous research. Moreover, when combined with the processor idle/shutdown state, the critical speed was widely used as the lower bound for voltage scaling in literature. In this paper, we show that this strategy might not always be more energy efficient than the traditional DVS strategy and there exists a dynamic tradeoff between these two strategies depending on the job’s work-demand to be finished within certain intervals. To effectively address this issue, we propose a unified approach that combines these two strategies to achieve better overall energy saving performance. Our approach determines the energy-efficient speeds for real-time jobs in their corresponding feasible intervals based on the threshold work-demand analysis. Our experimental results demonstrate that the proposed techniques significantly outperform previous approaches in the overall energy saving performance.

In this paper, the hybrid direct torque control (DTC) technique is proposed for controlling the speed of the induction motor (IM). The hybrid technique is the combination of an enhanced firefly algorithm (FA) and the adaptive neuro fuzzy inference system (ANFIS) technique. The performance of the FA is improved by updating the randomized parameter. Here, the genetic algorithm (GA) is utilized for updating the parameter and improved the performance of the FA. Initially, the actual torque and the change of toque are applied to the input of the enhanced FA and form the electromagnetic torque as a dataset. The output of the enhanced FA is given to the input of the ANFIS which is determined from the output of interference system. The dynamic behavior of the IM is analyzed in terms of the parameters such as the speed, torque, flux, etc. Based on the parameters, the motor speed is controlled by utilizing the proposed technique. Then the output of the ANFIS is translated into the stator voltage which is given to the input of the support vector machine (SVM). After that, the control signal is generated for controlling the speed of the IM. The proposed hybrid technique is implemented in the Matlab/Simulink platform. The performance analysis of the proposed method is demonstrated and contrasted with the existing techniques such as without controller, particle swarm optimization (PSO)-based ANFIS and FA-ANFIS controller.

A new cascadable voltage-input, current-output first-order all-pass filter and its applications in second-order filter and oscillator are presented. The proposed circuit employs a single active element namely extra-X current-controlled current conveyor (EX-CCCII) and only a single grounded capacitor. The circuit exhibits high input and high output impedances, so that the filter can be cascaded without additional buffers. The pole frequency is electronically tunable and the circuit requires no component matching constraints. Effects of nonidealities and parasitics are also discussed. As applications, a second-order transadmittance (TA)-mode all-pass filter and a quadrature oscillator are also realized using the proposed voltage-input, current-output first-order all-pass filter. These examples validate easy cascading feature of the proposed circuit. The validity of the proposed circuit is verified through PSPICE simulations using 0.25$\mu$m parameters with a supply voltage of $\pm 1.25$V.

This paper introduces a current-mode first-order all-pass filter (APF) and its application in quadrature oscillator (QO) based on CCCII. The proposed filter can provide inverting and noninverting all-pass functions with a same circuit topology, it uses two CCCIIs and one grounded capacitor. Moreover, the first-order all-pass filter was applied in current-mode sinusoidal quadrature oscillators with the design based on block diagrams. The introduced oscillators can provide four phase-quadrature signals which independently control the condition of oscillation (CO) and frequency of oscillation (FO). The proposed oscillators consist of three CCCIIs and two grounded capacitors. The proposed APF and QOs have high output impedance which can directly drive load without additional current buffer. In addition, they use only grounded capacitors which are very appropriate to future development into an integrated circuit. The results of PSPICE simulation program correspond to the theoretical analysis.

In this paper, we present the design and analysis of the proof mass for capacitive based MEMS accelerometers. A study was done to determine the parameters (length of hinge and number of combs) to be optimized for the MEMS accelerometer design. The proposed design can measure the acceleration in $x$-, $y$- and $z$-axes. The design features a proof mass with interdigitated fingers along each side. These interdigitated fingers act as parallel plate capacitors. Due to acceleration, capacitance changes along the comb drive. This change in capacitance can be used to monitor the acceleration. Analysis has been carried out with different comb width designs. Using the MEMS CAD tool CoventorWare, the structure has been designed, simulated and analyzed. The process flow for the fabrication has also been proposed for the above structure. Comparative study with several designs has been made and the efficient design parameters to be considered while designing MEMS accelerometer were proposed. Based on the study, a set of optimized design parameters for the comb accelerometer were reported.

This paper presents a compact tri-band waveguide bandpass filter using concentric multiple complementary split ring resonators (CSRRs). Two symmetrical concentric multiple CSRRs are placed on the transverse plane of a standard WR-90 rectangular waveguide at 8.41mm distance to achieve dual-pole, tri-band response. The proposed filter has been simulated using Ansoft High Frequency Simulation Software (version 14). Based on the simulated result the filter has been fabricated and tested. The measured result shows a dual-pole, tri-band, bandpass response with passbands at 8.04–8.2675GHz, 9.45–9.84925GHz and 11.35–12.005GHz, which is in good agreement with the simulated responses. The total length of the filter is 10mm, which makes it compact and light weight. An approximate equivalent circuit of the filter also has been provided.

Most digit-recurrence algorithms for division, such as the Sweeney–Robertson–Tocher (SRT) algorithm, have been used in order to take advantage of the redundant representations of the partial remainder. This way, full carry propagate additions are avoided, obtaining significant latency improvements. Furthermore, the delay corresponding to one division iteration is independent of the size of the operands. The most frequent redundant form for the partial remainders is the carry-save (CS) representation, which uses 2 bits of representation (carry and sum bits) for each bit of the partial remainder. This paper proposes radix-4 SRT dividers which use (3, 2) redundancy (3 bits of representation for 2 bits of the partial remainder) and (5, 4) redundancy (5 bits of representation for 4 bits of the partial remainder). The goal of using these representations is represented by a decreased cost due to the reduced number of sequential elements required to store the partial remainder. The proposed dividers use 2-bit carry propagate adders and 4-bit carry propagate adders to compute the new partial remainder. Thus, the full carry propagate addition is avoided, while the latency of one division iteration is independent of the operands’ size. The synthesis result for Xilinx Virtex-5 FPGA devices show that similar working frequencies are obtained for divider using the proposed redundant representation with respect to the conventional carry-save, while requiring up to 12% for (3, 2) representation and 18% for (5, 4) representation less sequential elements.

This paper presents two grounded MOS only active inductor circuits. Both circuits have only two MOS transistors and two biasing currents. Thus, the proposed active inductors provide small chip area, tunability, low power consumption with 150$\mu$W and 90$\mu$W, respectively. To analyze their performance, a second-order band-pass filter and a third-order high-pass filter structures are presented with low noise as 7.5nV/$\sqrt{\mathrm{\text{Hz}}}$ and 9.14nV/$\sqrt{\mathrm{\text{Hz}}}$, respectively. The designed active inductors and filters are simulated in 0.18$\mu$m CMOS process parameters using LTSPICE.

In this paper, the proposed hierarchical control scheme adds new control loop to control the reactive power reference by a fuzzy logic controller to have the benefit of increasing the system stability margins and moreover, eigenvalue, robustness and time delay analysis of proposed control scheme are presented. The reported droop-based control methods of VSI-based microgrids including hierarchical droop-based control scheme are limited to primary and secondary control levels while the proposed control scheme is completely analyzed so that the three hierarchical control levels modeled for both grid-connected mode and islanded mode. This scheme maintains the stability of microgrids not only for the small-signal events, but also for large-signal disturbances such as three phase and single phase to ground faults, heavy motor starting, etc. However, power sharing to loads and network is sufficiently done. To demonstrate the effectiveness of the proposed hierarchical controller, simulation studies have been performed on a microgrid consisting of four units of distributed generation with local loads and in presence of main grid using MATLAB/SIMULINK software and validated using OPAL RT real-time digital simulator.

This paper presents a novel method for the design of analog integrated circuit, making use of fixator–norator pairs for the performance design and biasing design. Fixators are the distinctive tools for setting a critical design parameter at a desired value whereas the pairing norator renders these critical parameters into adequate supporting components, mainly resistors. For analog ICs, active loads and current mirrors serve as supporting components. Hence, the use of fixator–norator pairs may abbreviate as defining the dynamic and static resistance of active loads and current mirrors that should be affirmative with a given design. The proposed methodology is illustrated by the use of a common emitter amplifier, a BJT differential amplifier, a MOS operational amplifier and a three-stage CMOS operational amplifier.

This paper presents a novel technique for the analysis of looped linear time-invariant electric circuits. This approach works in both time and Laplace domains; any type of elements could hence be incorporated. The circuit elements are partitioned into twofold classes of basic circuit and subsidiaries. The basic circuit is a spanning tree of the network, and the subsidiaries include circuit elements hypothetically removed from the looped electric circuit to open the loops. The subsidiaries include a suit of passive elements which might not even make any interconnected circuit. The circuit governing equations of flow and energy conservation are manipulated so that branch currents in the subsidiaries and branch voltages in the basic circuit are considered as independent variables to calculate passive element properties (impedance of all passive elements) directly. In contrast to existing methods, this technique is tailored for the circuit analysis in a reverse manner. As a complement for conventional circuit analysis techniques, this method can be taught in the undergraduate program to offer the students an alternative tool for the circuit analysis.

Crosstalk effects in multilayer graphene nanoribbon (GNR) interconnects for the future nanoscale integrated circuits are investigated with the help of ABCD parameter matrix approach for intermediate- and global-level interconnects at 11nm and 8nm technology nodes. The worst-case crosstalk-induced delay and peak crosstalk noise voltages are derived for both neutral and doped zigzag GNR interconnects and compared to those of conventional copper interconnects. The worst-case crosstalk delays for perfectly specular, doped multilayer GNR interconnects are less than 4% of that of copper interconnects for 1mm long intermediate interconnects and less than 7% of that of copper interconnects for 5mm long global interconnects at 8nm node. As far as the worst-case peak crosstalk noise voltage is concerned, neutral GNR interconnects are slightly better performing than their doped counterparts. But from the perspective of overall noise contribution, doped GNR interconnects outperform neutral ones for all the cases. Finally, our analysis shows that from the signal integrity perspective, perfectly specular, doped multilayer zigzag GNR interconnects are a suitable alternative to copper interconnects for the future-generation integrated circuit technology.

A Reversible Data Hiding technique by using histogram shifting and modulus operator is proposed in which secret data is embedded into blocks of the cover image. These blocks are modified by using modulus operator to increase the number of peak points in the histogram of the cover image which further increases its embedding capacity. Secret data is embedded in the original cover blocks of the cover image by using peak points of the predicted blocks, which are generated by using modulus operator. Peak Signal to Noise Ratio and PSNR-Human Visual System are used to show the human visual acceptance of the proposed technique. Experimental results show that the embedding capacity is high as compared to the capacity of existing RDH techniques, while distortion in marked images is also less as compared to distortion produced by these existing techniques.

With rapid expansions of wireless communications, requirements for transceivers that support concurrent multiple services are continuously increasing and demanding design of a concurrent low-noise amplifier (LNA) with low noise figure (NF), high gain, and high linearity over a wide frequency range for various wireless applications. The proposed work focuses on a concurrent multi-band LNA that works at navigational frequencies, namely, of 1.2GHz and 1.5GHz, wireless communication frequencies, namely, of 2.45GHz and 3.3GHz, dedicated short range communication (DSRC) frequency of 5.8GHz for the vehicular communication applications. This circuit has a distinct input matching network which resonates at all desired five frequency bands and is achieved by adapting frequency transformation method. To accomplish simultaneous reception of the desired penta-band, the output matching is designed with simple LC matching network with the aid of load-pull methodology.

In this paper, a new interleaved nonisolated bidirectional zero voltage switching (ZVS) dc–dc converter by using one three-windings coupled inductor is proposed. The proposed topology can provide high step-up and high step-down conversion ratios for boost and buck operations, respectively. Moreover, because of interleaving, the proposed converter has low input current ripple at low voltage side in both buck and boost operations. The proposed converter uses lower number of switches to have bidirectional power flow in comparison with other interleaved bidirectional converters. All used switches in the proposed converter are turned on under ZVS. The advantages of the proposed converter in comparison with the conventional interleaved converters are included in the capability of bidirectional power flow, ZVS operation for all switches and high step-up and high step-down voltage gain for boost and buck operations. In this paper, the proposed converter is analyzed completely and all equations of components are extracted as well as the ZVS conditions of all switches. Moreover, a comprehensive comparison between the proposed converter and conventional topologies is presented. To verify the accuracy performance of the proposed converter, the experimental results are given.