Journal of Circuits, Systems and Computers

Utilizing cloud computing, users can avail a compelling and effective approach for information sharing between collective individuals in the cloud with the facility of less administration cost and little maintenance. Security in cloud computing refers to procedures, standards and processes created to provide assurance for security of information in the cloud environment. In this paper, we project a secure data sharing method in cloud for dynamic members by producing keys for users using Logic Key Hierarchy (LKH) model, i.e., a tree-based key generation technique. We have generated this key using reverse hashing and one way hash-based technique so that no exiled user can predict the new key and new users cannot predict the old keys of the network group. From numerous experiments, this work is proved to be the best in maintaining forward secrecy, backward secrecy and group compromise attacks and consumes less computation cost compared to any other hash-based key generation techniques.

Time-interleaving has been a popular choice for multi-GHz analog-to-digital converters (ADCs) with a resolution of 8–14 bits. Unfortunately, inherent defects such as offset, gain, timing-skew mismatches among sub-ADCs degrade overall performance seriously. At present, the method for eliminating offset and gain mismatch is fairly straightforward; however, calibration for timing-skew is still in a state of exploration. A systematic overview of various calibration methods for timing-skew in time-interleaved ADCs (TI-ADCs) has been provided in this paper. Meanwhile, current state-of-the-art TI-ADCs recently are reported and several noteworthy trends can be observed from the statistical results.

Wireless sensor networks (WSNs) are a widely used solution for monitoring-oriented applications (e.g., water quality on watersheds, pollution monitoring in cities). These kinds of applications are characterized by the necessity of two data-reporting modes: time-driven and event-driven. The former is used mainly for continually supervising an area and the latter for event detection and tracking. By switching between both modes, a WSN can improve its energy efficiency and event-reporting latency, compared to single data-reporting schemes. We refer to those WSNs, where both data-reporting modes are required simultaneously, as multimodal wireless sensor networks (M2WSNs). In this paper, we present, from an energy-efficiency perspective, a review of switching mechanisms for M2WSNs. Besides, we explore two sophisticated techniques required in M2WSNs for further energy saving and event-reporting latency reduction purposes: duty-cycling and wake-up radio. We highlight future directions concerning switching and network management techniques for M2WSNs. To our knowledge, this review is first of its kind.

The distributed generation involving multiple photovoltaic sources and synthesizing high-quality ac voltage from those multiple dc sources are nascent research ambits. A host of multilevel inverters (MLIs) has been ascertained for performing above errand diligently, where the component count is obnoxious. The single phase seven-level inverter is an acquiescent compromise between the circuit complexity and the quality of the output. Further enhancement on the performance can be succored through optimizing dc link voltages and switching angles. This paper proposes a component count pruned MLI structure and also a refined genetic algorithm (RGA)-based optimization scheme for the computation of both dc link voltages and switching angles. Previous attempts for this problem have solved the switching angles with the objective of resulting minimum harmonic content in the staircase-shaped output voltage. The dc link voltage of each level is however assumed to be the same and constant. As an extension, RGA-based optimization of both dc link voltages and switching angles is triumphed. The harmonic profile of the proposed switching strategy is simulated and also corroborated by a hardware prototype. In practice, the proposed fundamental switched strategy is apposite, in which each dc voltage can be self-maintained and independently controlled. In addition, a method for designing the passive LC filter is also presented.

A novel multiband impulse radio ultra-wideband (MB-IR-UWB) transmitter with an energy-efficient and low-complexity pulse generator design technique compliant with the IEEE 802.15.4a standard is investigated in this paper. This transmitter is made up of a new differential narrow triangular pulse generator, a new multiband voltage-controlled oscillator (VCO), an active mixer and a variable-gain power amplifier (PA). It operates at 14 UWB bands and generates an output signal with the duration of 3ns, more than 500MHz of channel bandwidth and more than 20dB of sidelobe suppression, while achieving an average energy efficiency of 51.36 pJ/pulse from 1.4-V supply. Improving spectral flexibility and worldwide compliance is the major contribution brought by this paper to make this circuit as a multifunction wireless device well suited for low-cost, low-power multiband applications.

This paper proposes a novel surrogate-assisted multi-objective evolutionary algorithm, MOEA-ATCM, to solve expensive or black-box multi-objective problems with small evaluation budgets. The proposed approach encompasses a state-of-the-art MOEA based on a nondominated sorting genetic algorithm assisted by multi-fidelity optimization methods. A high-fidelity attribute tendency (AT) surrogate model was used to construct a linear decision space by introducing the knowledge of the objective space. A coarse model (CM) based on the AT model and correlation analyses of the objective functions and decision attributes were used to predict the Pareto dominance for candidates in the new decision space constructed by the AT model. Two major roles of MOEA-ATCM were identified: (1) the development of a new multi-fidelity surrogate-model-based method to predict Pareto dominance in a decision space that was then applied to MOEA, which does not need to dynamically update surrogate models in the optimization process and (2) the development of a Pareto dominance prediction method to obtain good nondominated solutions of expensive or black box problems with relatively few objective function evaluations. The advantages of MOEA-ATCM were verified by mathematical benchmark problems and a real-world multi-objective parameter optimization problem.

Recent years have witnessed a surge of interest in semi-supervised learning-based object detection. Object detection is usually accomplished by classification methods. Different from conventional methods, those usually adopt a single feature view or concatenate multiple features into a long feature vector, multiview graph spectral learning can attain simultaneously object classification and weight learning of multiview. However, most existing multiview graph spectral learning (GSL) methods are only concerned with the complementarities between multiple views but not with correlation information. Accurately representing image objects is difficult because there are multiple views simultaneously for an image object. Thus, we offer a GSL method based on multiview canonical correlation analysis (GSL-MCCA). The method adds MCCA regularization term to a graph learning framework. To enable MCCA to reveal the nonlinear correlation information hidden in multiview data, manifold local structure information is incorporated into MCCA. Thus, GSL-MCCA can lead to simultaneous selection of relevant features and learning transformation. Experimental evaluations based on Corel and VOC datasets suggest the effectiveness of GSL-MCCA in object detection.

In this paper, a novel seven-level Quasi-Z-Source-based $T$-type inverter (7LqZST${}^2\text{I}$) is proposed. The proposed inverter is an upgrade of Quasi-Z-source (qZs) network and seven-level $T$-type inverter. The 7L qZST${}^2\text{I}$ comprises of three qZs-based impedance networks, two bidirectional switches and an $H$-bridge inverter. It owns the advantages of reduced switch count, improved output voltage gain, enhanced reliability and better quality of output voltage and current. The performance of the proposed topology is tested for two different pulse width modulation techniques based on shoot-through control. The first technique offers simple control and operated at a fixed shoot-through duty cycle for realizing output voltage level. The second technique facilitates independent control of each qZs network dc-link voltage and they can be operated at different shoot through duty cycle which overcomes the limitation of first technique with better quality in output voltage. The detailed operation of the proposed topology and control schemes have been elaborated for different switching states for each output voltage level generation. Extensive simulation and experimentation are performed for both the switching schemes to verify their performance under steady state and dynamic conditions. Furthermore, a brief comparison is constructed to highlight the merits of the proposed inverter with conventional topologies.

The automatic recognition of QRS complexes in an Electrocardiography (ECG) signal is a critical step in any programmed ECG signal investigation, particularly when the ECG signal taken from the pregnant women additionally contains the signal of the fetus and some motion artifact signals. Separation of ECG signals of mother and fetus and investigation of the cardiac disorders of the mother are demanding tasks, since only one single device is utilized and it gets a blend of different heart beats. In order to resolve such problems we propose a design of new reconfigurable Subtractive Savitzky–Golay (SSG) filter with Digital Processor Back-end (DBE) in this paper. The separation of signals is done using Independent Component Analysis (ICA) algorithm and then the motion artifacts are removed from the extracted mother’s signal. The combinational use of SSG filter and DBE enhances the signal quality and helps in detecting the QRS complex from the ECG signal particularly the R peak accurately. The experimental results of ECG signal analysis show the importance of our proposed method.

This paper presents a high precision output impedance calibration technique for source-series terminated (SST) transmitter. Unlike the conventional impedance calibration technique using a digital method, the proposed impedance calibration employs the analog method to implement the impedance calibration. Therefore, there is no trade-off between area overhead and precision of calibration. The proposed analog impedance calibration circuit has three analog impedance control loops, namely, pull-up loop, pull-down loop and shunt-loop. Each loop is composed of a high gain amplifier and a slice-based unit. To reduce the hardware, the shunt loop utilized a slice unit replication design to achieve the shunt-slice calibration. These loops send output voltage to the SST transmitter when they reached stability. Fabricated in 55nm CMOS technology, the power consumption of the calibration circuit is 1.35mW and the total area is 61$\mu$m*83.1$\mu$m, which consumes 6.3% of the total power consumed by the transmitter and occupies 25% of the total area occupied by the complete transmitter. The post-layout simulation result shows that the maximum impedance calibration error of the three loops is less than 0.02%.

Experimental study on noise-induced synchronization of crystal oscillators is presented. Two types of circuits were constructed: one consists of two Pierce oscillators that were isolated from each other and received a common noise input, while the other is based on a single Pierce oscillator that received a same sequence of noise signal repeatedly. Due to frequency detuning between the two Pierce oscillators, the first circuit showed no clear sign of noise-induced synchronization. The second circuit, on the other hand, generated coherent waveforms between different trials of the same noise injection. The waveform coherence was, however, broken immediately after the noise injection was terminated. Stronger perturbation such as the voltage resetting was finally shown to be effective to induce phase shifts, leading to phase synchronization of the Pierce oscillator. Our study presents a guideline for utilizing noise to synchronize clocks of multiple CPU systems, distributed sensor networks, and other engineering devices.

Live digital video is a valuable source of information in security, broadcast and industrial quality control applications. Motion jitter due to camera and platform instability is a common artefact found in captured video which renders it less effective for subsequent computer vision tasks such as detection and tracking of objects, background modeling, mosaicking, etc. The process of algorithmically compensating for the motion jitter is hence a mandatory pre-processing step in many applications. This process, called video stabilization, requires estimation of global motion from consecutive video frames and is constrainted by additional challenges such as preservation of intentional motion and native frame resolution. The problem is exacerbated in the presence of local motion of foreground objects and requires robust compensation of the same. As such achieving real-time performance for this computationally intensive operation is a difficult task for embedded processors with limited computational and memory resources. In this work, development of an optimized hardware–software co-design framework for video stabilization has been investigated. Efficient video stabilization depends on the identification of key points in the frame which in turn requires dense feature calculation at the pixel level. This task has been identified to be most suitable for offloading the pipelined hardware implemented in the FPGA fabric due to the involvement of complex memory and computation operations. Subsequent tasks to be performed for the overall stabilization algorithm utilize these sparse key points and have been found to be efficiently handled in the software. The proposed Hardware–Software (HW–SW) co-design framework has been implemented on Zedboard FPGA platform which houses Xilinx Zynq SOC equipped with ARM A9 processor. The proposed implementation scheme can process real-time video stream input at 28 frames per second and is at least twice faster than the corresponding software-only approach. Two different hardware accelerator designs have been implemented using different high-level synthesis tools using rapid prototyping principle and consume less than 50% of logic resources available on the host FPGA while being at least 30% faster than contemporary designs.

The paper is dedicated to the linear time-invariant analog electronic circuits. It deals with the problem of modeling of the circuits in the $z$-domain. The model put forward in this paper enables solving different issues with the analysis of linear dynamic circuits. The model’s usefulness to fault diagnosis is emphasized in the paper, especially its application to multiple soft fault diagnosis of linear circuits. To make such diagnosis possible, the node equations with unknown node voltages and the diagnosed parameters are used. The set of actual values of the verified parameters is achieved by solving an appropriate system of algebraic nonlinear equations associated to the node equations. It can be determined using the Newton algorithm with adaptive choice of damping parameter. The diagnosis method is adjusted to real conditions by considering the deviations of the healthy parameters inside their tolerance scopes. Two real-life electronic circuits are considered to illustrate the method.

In this paper, we propose a resource/performance tradeoff algorithm for task scheduling of parallel reconfigurable architectures. First, it uses unlimited resources to generate an optimal scheduling algorithm. Then, a relaxation algorithm is applied to satisfy the number of resources under increasing minimum performance. To demonstrate the performance of the proposed algorithm, we not only compare the existing methods with standard benchmarks but also implement on physical systems. The experimental results show that the proposed algorithms satisfy the requirements of the systems with limited resources.

It is of great importance to model the behavior of nonlinear systems in a distributed fashion using wireless sensor networks (WSNs) because of its computation and energy-efficient data processing. However, least squares methods have been previously employed to estimate the parameters of Volterra model for modeling nonlinear systems. Still, it is more convenient and advantageous to use in-network distributed identification strategy for real-time modeling and control. In this context, a black-box model with generalized structure and remarkable modeling ability called Volterra–Laguerre model is considered in which distributed signal processing is employed to identify the nonlinear systems in a distributed manner. The model cost function is expressed as a separable constrained minimization problem which is decomposed into augmented Lagrangian form to facilitate the distributed optimization. Then, alternating direction method of multipliers is employed to estimate the optimal parameters of the model. Convergence of the algorithm is guaranteed by providing its mean stability analysis. Simulation results for a nonlinear system are obtained under the noisy environment. These results are plotted against the results of noncooperative and centralized methods, demonstrating the effectiveness and superior performance of the proposed algorithm.

A new approach for realizing sinusoidal signal with quadrature property is proposed, which employs simple analog building blocks and facilitates easy tuning of the oscillation frequency, through a gain factor. The proposed approach is used for realizing a novel quadrature oscillator circuit, which requires three current feedback operational amplifiers and passive components. The proposed circuit provides outputs at low impedance terminals, and benefits from easy control over the frequency of oscillation (FO), which depends on resistive ratio, rather than absolute resistor values. The frequency control is also independent of the condition of oscillation (CO). The nonideal effects and the parasitic studies are presented. The verification of the proposed realization scheme for quadrature oscillators and the new circuit is carried out through both simulation studies and experimental results, using the commercially available chips.

A novel compact coplanar waveguide (CPW)-fed planar monopole antenna with triple-band operation is presented for simultaneously satisfying the LTE 2600, WiMAX, WLAN and X-band applications. It is printed on a single-layered FR4 substrate. In this paper, the proposed antenna, which occupies a small volume of $30\times 28\times 0.8$mm³ including the ground plane, is simply composed of a CPW-fed monopole with U-, L- and T-shaped slots. By carefully selecting the lengths and positions of both L-shaped and U-shaped slots, a good dual notched band characteristic at center-rejected frequencies of 3.10GHz and 4.50GHz can be achieved, respectively. The T-shaped slot is etched on the radiating element to excite a resonant frequency in the 7GHz band. Then, to prove the validation of the typical design, a prototype model is fabricated and measured. The experimental result shows that the three frequency bands of 2.31–2.80GHz (490MHz), 3.37–3.84GHz (470MHz) and 5.04–7.94GHz (2900MHz) can successfully cover the desired bandwidths of LTE2600/WiMAX (3.50/5.50GHz)/WLAN (5.20/5.80GHz) and the X-band communication systems (7.1-GHz operation). The principal applications of the X-band are radar, aircraft, spacecraft and mobile or satellite communication system. Nearly omnidirectional and bidirectional radiation patterns of the triband antenna are observed in both H- and E-planes, respectively. In addition, a reasonable gain over the operating bands has been obtained. Indeed, the good agreements between simulation and measurement results have validated the proposed structure, confirming its potential for multiband wireless communication services.

This paper introduces a concurrent computing technique for the acceleration of digital stochastic measurement simulations. The digital stochastic measurement presents an advanced methodology based on the specific parallel hardware structure, utilized for an orthogonal transformation calculus/decomposition. Methodology is analyzed in detail, starting from the very basic idea, toward recent references, covering main research directions and trends. An oversampling nature of the evaluated digital stochastic measurement, along with demanding arithmetic requirements, implies exhausting simulation complexity. As a test case, several typical power grid signals were harmonically analyzed through a discrete Fourier transformation based on the proposed methodology. A harmonic decomposition was simulated with several levels of computing concurrency. Through all the simulated scenarios main success criterion was model accuracy, while the parameter used for selection of the optimal simulation computing technique was the overall calculus speed. Final results exposed thread pool computing technique as an optimal simulation platform.