Journal of Circuits, Systems and Computers

Recent decades have seen significant progresses in the field of power amplifiers (PAs). In order to present the evolution of the field, this paper shows the development trends of the PA research based on the statistical analysis from 1970 to 2017. The brief history of radio frequency (RF)/microwave PAs and a comprehensive review on the evolution of RF/microwave PAs are presented. The state-of-the-art PAs thus far based on the statistical analysis in terms of the figure of merit (FoM) of RF/microwave PAs have been discussed in this paper. A quantitative relationship of trade-off of PA performance metrics is proposed, and the potential room for improvement of the performance of the PAs is also revealed.

To improve the classification performance of motor imagery (MI) based brain-computer interfaces (BCIs), a new signal processing algorithm for classifying electroencephalogram (EEG) signals by combining filter bank and sparse representation is proposed. The broadband EEG signals of 8–30Hz are segmented into 10 sub-band signals using a filter bank. EEG signals in each sub-band are spatially filtered by common spatial pattern (CSP). Fisher score combined with grid search is used for selecting the optimal sub-band, the band power of which is employed for designing a dictionary matrix. A testing signal can be sparsely represented as a linear combination of some columns of the dictionary. The sparse coefficients are estimated by $l_1$ norm optimization, and the residuals of sparse coefficients are exploited for classification. The proposed classification algorithm was applied to two BCI datasets and compared with two traditional broadband CSP-based algorithms. The results showed that the proposed algorithm provided superior classification accuracies, which were better than those yielded by traditional algorithms, verifying the efficacy of the present algorithm.

In this paper, a novel circuit method is proposed to reduce 1/f³ (close-in) phase noise in a cross-coupled LC Voltage Control Oscillator (VCO) by suppressing flicker noise power of the tail transistor. Using an added resistor between drain and gate of the tail transistor, that works as a negative feedback, the tail transistor flicker noise is suppressed, and therefore, the 1/f³ output phase noise is reduced by 5.7dB. Also, the added resistor helps in better tail current shaping for phase noise reduction. The proposed oscillator is designed in a 0.18$\mu$m CMOS technology with 1.8V supply and 3.6mW power consumption. Post-layout simulations predict a phase noise of $-104$dBc/Hz for the proposed oscillator at 100KHz offset from 3.1GHz carrier frequency. Mathematical analysis is included in the paper for confirmation of the phase noise performance enhancement. The Figure of Merit (FOM) of the proposed oscillator is 188.3 and 190.6dBc/Hz at 100KHz and 1MHz offsets, respectively.

In this paper, a wideband full-360^o phase shifter with 6 bits of accuracy has been designed and simulated with minimal root mean square (RMS) phase error. The proposed phase shifter deployed a feed forward path including a frequency-to-voltage converter (FVC) to minimize the mismatch in quadrature generation to eventually reduce the RMS phase error for S-band (2–4GHz) applications. The designed phase shifter in 180nm CMOS technology achieves an RMS phase error in the range of 0.607–1.18^∘ with $-50$dBm input signal over 2–4GHz frequency band. With lower input signal of $-75$dBm, the RMS phase error is 0.621–1.34^∘ for 2–4GHz input frequency. The proposed phase shifter shows an RMS amplitude error less than 0.41dB over 2–4GHz frequency. The 1-dB compression point ($P_{-1\mathrm{\text{dB}},\mathrm{\text{CP}}}$) of the proposed phase shifter is $-23$dBm. The proposed wideband phase shifter draws 32 mA from 1.8 supply voltage. It occupies an active area of only 0.025mm², due to active design without any inductor.

This paper tackles the problem of Fault Tolerant Control (FTC) for Wind Turbine System. Motivated by the Model Reference Adaptive Control (MRAC) and the Particle Swarm Optimization Algorithm (PSOA), the main contribution of this work is to provide online tuning for the wind turbine controller. In order to achieve the required system performances, even during components and/or system faults, our proposed strategy takes care of an adaptive controller in which the desired performance is expressed in terms of a reference model. The controller parameter adjustments are made using the stability theory that involves the gradient function and the Lyapunov function. Moreover, the minimization of the fitness function of PSOA allows convergence of the proposed MRAC to an optimal point, owing to redistribution of the control signals when a failure or noise occurs. The simulation results have shown good performance than some existing approaches in the literature.

In this paper, a compact low-power, high-speed, low-error four-quadrant analog multiplier is proposed using a new simple current squarer circuit. The new squarer circuit consists of an NMOS transistor, which operates in saturation region, plus a resistor. The proposed multiplier has a balanced structure composed of four squarer cells and a simple current mirror. This multiplier also has the important property of not using bias currents which results in greatly reduced power. The performance of the proposed design (for passive and active realization of the resistors) has been simulated using HSPICE software in 0.18$\mu$m TSMC (level-49) CMOS technology. Simulation results with $\pm 0.7$-V DC supply voltages show (for passive realization) that the maximum linearity error is 0.35%, the $-3$dB bandwidth (BW) is 903MHz, the total harmonic distortion (THD) is 0.3% (at 1MHz), and the maximum and static power consumption are $139.25\mu$W and $14.5\mu$W, respectively. Also, post-layout simulation results are extracted, which give the maximum linearity error as 0.4%, the $-3$dB BW as 657MHz and the THD as 0.35%, as well. Moreover, Monte Carlo analysis are performed to verify the satisfactory robustness and reliability of the proposed work’s performance.

This work presents the design and test of a switched-cap 3D DC/DC converter able to work up to 60V. The switches and the control circuits are integrated single-chip in a high-voltage (HV) MOS technology, and the passive devices are stacked on top of the chip. As an innovation versus the state-of-the-art, the work first presents the design of integrated passive devices, based on through silicon vias (TSV) MOS-compatible technology, which are suitable for switching converter applications up to 60V. Then, the implementation and experimental characterization of the switched-cap 3D DC/DC is proposed, with the silicon TSV capacitors stacked on top of the 0.35$\mu$m HV-MOS die. Compared with the state-of-the-art, the proposed 3D DC/DC converter is a compact circuit, able to directly regulate a wide input voltage range (from 6V to 60V) to a 5V, 2W output. Hence, it is suitable to supply low-power loads, such as control units and/or sensors, directly from the 48V power line available in hybrid vehicles or telecom and networking systems.

This paper devises a design named brushless doubly fed induction generator (BDFIG) with a fault ride-through enhancement that employs upgraded field-oriented control (FOC) scheme. The DFIG is most suitable for wind energy conversion system (WECS) because it has an amicable establishment, economical operation and promising characteristics. A WECS based on two BDFIGs connected electrically in parallel and mechanically in series, excited by a three-phase inverter and controlled as variable speed, is described. For enhancing power quality and power flow capability, static compensator (STATCOM) has been incorporated in the proposed configuration. The comparative analysis on performance has been carried out with the existing proportional-integral (PI) controller and self-tuning fuzzy logic controller (STFLC) for the proposed configuration under varying wind speed. In this paper, the fuzzy controller is designed to adapt PI parameters Kp and Ki, in order to reduce at least some inherent characteristics (overshoot, response time, etc.) of the error between the reference and system response. The digital simulation results claim that the FLC-based controller can offer an attractive and feasible control for the proposed WECS integrating two BDFIGs.

Adopting the moduli set $\{2^{n+1}-1,2^n,2^n-1\}$ for different DSP applications instead of the traditional moduli set $\{2^n+1,2^n,2^n-1\}$ has the advantage of excluding modulus $2^n+1$. A multiply-and-accumulate modulo $2^n+1$ unit is more demanding than a modulo $2^{n+1}-1$ unit, which signifies the importance of this adoption. This paper introduces a new design for a scaling unit “Scaler”, that deals with the arithmetic-friendly residue number system (RNS) moduli set $\{2^{n+1}-1,2^n,2^n-1\}$. The scaling factor is the power-of-two moduli $2^n$. The scaling algorithm is based on the mixed-radix conversion (MRC) technique, which converts RNS-based representation into a weighted representation. The proposed approach is compared with other functionally-identical or functionally-similar scalers that perform scaling for the same moduli set under consideration or for the moduli set $\{2^n+1,2^n,2^n-1\}$. The comparison is carried using theoretical unit-gate approach and experimental VLSI layout approach. The proposed scaler is shown to be more area and power-efficient than recently published competitive works.

Recent advances in network speeds for exchanging multimedia data over insecure networks has resulted in an increased interest in steganography techniques. These techniques are usually evaluated based on their performance in three attributes; namely, capacity, imperceptibility, and robustness. Each of these attributes has its own measurement metric. Hence, comparing two different steganography schemes based on these individual metric tools becomes inconsistent. In this paper, a novel measurement metric tool is introduced for benchmarking steganography schemes. This new tool, named the “Combined Capacity-Quality-Robustness Effectiveness” (CCQRE) metric, combines the three opposing attributes of a steganography system into one conglomerate performance measure. Comparative results demonstrate the effectiveness of the proposed CCQRE metric for benchmarking various steganography schemes based on the researcher’s interest in capacity, imperceptibility, or robustness.

Termination transformation theorem (TTT) proposed in this work transforms a doubly complex terminated microwave power transfer network (PTN) to an equivalent doubly resistively terminated termination transformed network (TTN) which is essentially a filter network. In this work, the transducer power gain (TPG) formula, Tgen, based on S and transmission (ABCD) parameters for the PTN have been restudied from the classical literature. Then, a new TPG formula, Tgen1, based on the newly proposed TTT has been derived using the transformed TTN network. To be able to show the validity of the proposed TTT, the newly derived TPG formula Tgen1 and the classical TPG formula Tgen have been computed within the scope of an example PTN design. The theorem has been proved mathematically, and experimentally as well with the aid of a Matlab code. The performance plots yielded from the Matlab code have clearly shown that both TPG formulae, i.e., Tgen and Tgen1, are in complete agreement with each other. In that sense, the proposed TTT might be considered as an alternative and helpful technique to be used in microwave engineering.

A Fault-Resistant scheme has been proposed to secure the Advanced Encryption Standard (AES) against Differential Fault Analysis (DFA) attack. In this paper, a hybrid countermeasure has been presented in order to protect a 32-bits AES architecture proposed for resource-constrained embedded systems. A comparative study between the most well-known fault detection schemes in terms of fault detection capabilities and implementation cost has been proposed. Based on this study, we propose a hybrid fault resistant scheme to secure the AES using the parity detection for linear operations and the time redundancy for SubBytes operation. The proposed scheme is implemented on the Virtex-5 Xilinx FPGA board in order to evaluate the efficiency of the proposed fault-resistant scheme in terms of area, time costs and fault coverage (FC). Experimental results prove that the countermeasure achieves a FC with about 98,82% of the injected faults detected during the 32-bits AES process. The area overhead of the proposed countermeasure is about 14% and the additional time delay is about 13%.

Space-Time Adaptive Processing (STAP) can harness the efficacy of interference and clutter significantly. Calculations of the STAP weights involve solving linear equations which require very intensive computations. In this paper, the QR decomposition (QRD) using the modified gram-schmidt (MGS) algorithm is parameterized with vector size to create a trade-off between the hardware resources utilization and computation time. To achieve an efficient floating point structure, the proposed architecture of QRD-MGS algorithm is simulated and implemented in two modes: single-vector and multi-vector. Results show that the multi-vector method can lead to a high-performance design with higher operating frequency, lower power consumption, and less resource utilization than the single-vector method. For example, Modelism simulations show that the decomposition of a $12\times 51$ matrix with vector size of 17 takes 7.86$\mu$s with the maximum clock frequency of 282MHz, for implementation on the Arria10 FPGA. In real STAP applications, the matrix sizes are too large to be fit on FPGAs and the update rate of the weights are high. Therefore, this method can fit any matrix in the contemporary FPGAs with an acceptable update rate.

The state-of-the-art high efficiency video coding (HEVC/H.265) adopts the hierarchical quadtree-structured coding unit (CU) to enhance the coding efficiency. However, the computational complexity significantly increases because of the exhaustive rate-distortion (RD) optimization process to obtain the optimal coding tree unit (CTU) partition. In this paper, we propose a fast CU size decision algorithm to reduce the heavy computational burden in the encoding process. In order to achieve this, the CU splitting process is modeled as a three-stage binary classification problem according to the CU size from $64\times 64$, $32\times 32$ to $16\times 16$. In each CU partition stage, a deep learning approach is applied. Appropriate and efficient features for training the deep learning models are extracted from spatial and pixel domains to eliminate the dependency on video content as well as on encoding configurations. Furthermore, the deep learning framework is built as a third-party library and embedded into the HEVC simulator to speed up the process. The experiment results show the proposed algorithm can achieve significant complexity reduction and it can reduce the encoding time by 49.65%(Low Delay) and 48.81% (Random Access) on average compared with the traditional HEVC encoders with a negligible degradation (2.78% loss in BDBR, 0.145dB loss in BDPSNR for Low Delay, and 2.68% loss in BDBR, 0.128dB loss in BDPSNR for Random Access) in the coding efficiency.

The design proposed and fabricated in this paper is a slotted wide-band rectenna with the inclusion of Defected Ground Structure (DGS) which can harvest RF energy in the frequency range of 5.336–6.194GHz with a center frequency of 5.8GHz. For the development of antenna, FR4 substrate having a dielectric permittivity of 4.3 has been adopted. Two parallel slots on the patch are incorporated on either side of the feed line to obtain the wide-band structure. Dumbbell-shaped DGS is also incorporated exactly underneath the feed line to increase the gain of the antenna. HSMS-285C Schottky diode has been used for the implementation of the rectifier circuit and a Greinacher voltage doubler has been chosen. ADS design software has been used for rectifier simulation and CST has been used for the designing of the antenna. Current behavior on the patch can be investigated to explore the wide-band mechanism. The antenna operates in the frequency range of 5.336–6.194GHz and with VSWR less than 2, which corresponds to 16.07% impedance bandwidth. The antenna achieves a gain of 6.189dB and a directivity of 8.776dBi. The conversion efficiency of the rectifier was optimized to 75% at 5.8GHz. The proposed design gave an output of 3.2V which can be used under numerous energy harvesting and wireless power transmission applications.

Meminductor has attracted more and more attention as the new memory element. In this paper, a new generic meminductor model is proposed and analyzed. Its emulator is designed and its pinched hysteresis loop is presented. Based on the established meminductor and using a traditional capacitor and resistor, a new simple chaotic circuit presenting double-scroll chaotic attractors is proposed and its dynamical behaviors including phase portrait, Lyapunov exponents, Poincare mapping, power spectrum, bifurcation and the sensibility of initial value are analyzed. Meanwhile, it has been found that hidden attractors and transient chaotic phenomena under different initial value. Finally, the hardware circuit for the proposed simple double-scroll chaotic system is constructed and some experimental results are presented for validating the correctness of the theoretical analysis.

Hardware Trojan has become a major threat to the security and trustworthiness of integrated circuit (IC) employed in critical applications. Due to the presence of process variations and measurement noises, all existing side-channel Trojan detection approaches suffer from low detection sensitivity or even false negatives with increasing circuit size and decreasing Trojan size. In this paper, we propose a statistical test generation approach based on mutation analysis, which generates a set of test vectors aiming at activating the hardware Trojan inserted into the low activity nodes. Such approach not only enhances the controllability of low activity nodes through increasing the switching activity of it, but also improves the observability by propagating the artificial designed errors introduced by the mutant to the outputs. Simulation results of a set of ISCAS’85 and ISCAS’89 benchmark circuits show that the proposed approach improves the activity of low activity nodes 463% at most compared with the Multiple Excitation of Rare Occurrence (MERO) approach and increases the Trojan coverage with 84.08% reduction in test length. Moreover, the test vectors generated by the proposed approach and the MERO approach, respectively, are exerted to the circuit under test. Experimental results demonstrate that the Mahalanobis distance margin of the proposed approach is much greater than the MERO approach, and thus provide a comparable robustness with decreasing Trojan size.

In this paper, two novel low-profile monopole antennas are presented for simultaneous operation in GPS (Global Positioning System), WLAN (Wireless Local Area Network) and WiMAX (Worldwide Interoperability for Microwave Access) applications. The antennas constitute of a T-shaped microstrip feed line and directly coupled strips to generate multiple bands. The proposed antennas are printed on one side of a low-cost FR4 epoxy substrate and partial ground plane (metal plane is etched partially) are fabricated on the other side of the substrate. The overall dimension of antenna is $50\times 35\times 1.6$mm³. Measured results show that the antenna1 (quad band) covers the four distinct operating bands of 320MHz (2.17–2.49GHz), 190MHz (3.31–3.50GHz), 270MHz (5.18–5.45GHz) and 700MHz (5.5–6.20GHz). Antenna2 (penta band) covers the frequency bands of 1.29–1.98GHz (center frequency 1.61GHz), 2.78–2.91GHz (center frequency 2.83GHz), 3.59–3.94GHz (center frequency 3.75GHz), 5.15–5.33GHz (center frequency 5.24GHz) and 5.39–6.06GHz (center frequency 5.56GHz). The detail antenna design and parametric analyses are discussed in steps. The characteristic of radiation pattern and gain are measured. The measured and simulated results are in good agreement. The antennas are designed using a simulation software HFSS v.15.