Journal of Circuits, Systems and Computers

In this paper, a new data transmission method, named Uni-Pulse Harmonic Modulation (PHM), is presented and its concept is mathematically analyzed using the relations of inductive links. In this type of modulation, the Uni-Pulse passing through the primary coil generates an oscillation in the secondary coil, corresponding to its positive edge, and its negative edge is able to damp this oscillation. The Uni-Pulse passing the primary coil gives the opportunity to use a half-bridge driver instead of full-bridge driver and hence the chip area is desirably reduced. For implementing the proposed modulation technique, two half-bridge driver circuits are suggested that are controlled by series of transistors and transmission gates occupying 900$\mu$m² and 737.87$\mu$m² of chip area, respectively. Another merit of the proposed transmitters, besides their occupying low chip area, is that they can transmit data at the rate of 40MHz, while the received frequency is set at 66.6MHz. Therefore, the high amount of 60% is obtained for the data rate to carrier frequency ratio. Designed in a standard 0.18-$\mu$m CMOS process, the proposed circuits operate at 1.8V supply voltages with consuming almost 400pj energy for transmitting each data bit.

A digital-based Pseudo-differential Schmitt trigger is proposed in this paper which is suitable for ultra-low voltages and pure digital integrated circuit technologies. The proposed Schmitt trigger is implemented according to the design procedure of an analog Schmitt trigger and only using digital CMOS inverters. It is composed of a differential comparator consisting of two CMOS inverters and a cross-coupled inverter pair positive feedback which has simultaneously two outputs of noninverting and inverting. The proposed circuit is the only digital Schmitt trigger which operates in differential mode and its hysteresis center can be changed by the input voltage. Implementing the circuit in digital-based allows the proposed Schmitt trigger to operate in 0.4V ultra-low-voltage. Principle operation of the proposed circuit is discussed theoretically and using formulas and its performance is verified by simulation in TSMC 0.18$\mu$m CMOS process. The proposed circuit occupies only $10\times 9.8$$\mu$m² chip area due to the very low number of transistors. The hysteresis width of the proposed Schmitt trigger is 205mV and consumes only 6.64nW power.

In recent years, iris recognition is one of the most widely used techniques for person identification. Automatic iris identification implies a comparison of query iris image with iris entries in a large database to determine the identity of the person. In this paper, we propose a straightforward and effective algorithm for the classification of irises into several categories according to the iris texture characteristics. The goal of the classification is to identify and retrieve a smaller subset of the large database and to narrow down the search space. In this way, the response time of the iris recognition system could be significantly improved. We analyzed several cases for dividing the whole database (we used UPOL, CASIA, and UBIRIS databases) into up to eight subsets and calculated the time savings. The simulation results illustrate the potential of the proposed classification method for large-scale iris databases.

This paper presents two new voltage-mode sinusoidal oscillators based on voltage differencing inverting buffered amplifier (VDIBA). The first proposed circuit exhibits independent and electronic control of oscillation condition by using the bias current of the VDIBA. The proposed configuration contains only single VDIBA, two grounded capacitors and two resistors, which are the least number of active components and the minimum number of passive components necessary for realizing voltage-mode oscillator topology. The second proposed circuit exhibits independent and electronic control on the condition of oscillation without affecting the oscillation frequency by adjusting the separate bias currents of the VDIBAs. The proposed configuration contains two VDIBAs, two grounded capacitors and one resistor, which can provide four quadrature voltage outputs simultaneously. Both proposed circuits enjoy only two grounded capacitors, which are suitable for monolithic integration. HSpice simulations and experimental results are included to confirm the theoretical analysis.

The lifetime reliability of processors has become a major design constraint in the dark silicon era. Processor reliability issues are mainly due to design defects and aging. Unlike design defects, however, aging faults gradually accumulate over time. Many methods have recently been proposed to monitor the performance degradation of circuits. In this study, an architectural solution that extends the circuit-level age monitoring to processor stages is proposed for monitoring performance degradation. When degradation of a stage quantified as delay of half of the reference clock occurs, a self-repairing mechanism is triggered. This mechanism configures an field programmable gate array (FPGA), which takes over the functions of the degraded unit. The proposed self-repairing mechanism is applied to the stages of the processor data-path. This method (SeRA) has lesser area overhead compared with the state-of-art solutions.

In this paper, the FPGA implementation of the generalized parallel two-box (GPTB) model is proposed. The blocks such as multipliers, complex magnitude calculator, and magnitude powers calculator have been utilized to implement the GPTB model. In the implementation of the proposed model, a total of 30 complex multipliers, 56 noncomplex multipliers and 56 adders were used. The GPTB DPD model has been implemented by using System Generator and Vivado software. The FPGA with a part number of xc7vx690t-3 from Xilinx has been employed to implement the model. The simulation results demonstrate the correctness of the implemented model in Vivado. Also, the verification of the GPTB model is accomplished by means of the simulation of the transmitter excited by QAM signals in the ADS software. The measure of an adjacent channel power ratio (ACPR) decreased by about 16dB as a result of the simulation.

This paper deals with the development of a realistic power line channel simulator wherein power line communication devices can be tested before implementation to meet the massive need of data transfer. The statistics of the noise follow the experimentally observed in different sites, namely the time-varying non-white power spectral densities (PSDs) of the background noise and a target non Gaussian amplitude distribution. The procedure based on the inverse cumulative distribution function method of generation of random numbers and iteratively updating a target spectrum necessitates knowledge of a maximum of 17 parameters for successful implementation and has been validated for three sites in the low-frequency ($<$500kHz) and high-frequency (1–30MHz) bands. The average percentage errors in prediction of the mean of the channel capacity (CC) are 12.68% and 10.66% in the two bands, respectively. The minimum correlations of the distribution of BER of OFDM in a channel corrupted by the simulated and observed noises are is 0.883 and 0.801 in the two bands which are high compared to 0.422 and 0.355, respectively, when the requirement of a target amplitude distribution is neglected. With low-frequency noise emulated by a data acquisition card, an average percentage error of 11.82% in the CC and a correlation of 0.867 (against 0.498) in BER are obtained. The noise thus generated can be used as a testbed for system testing, instead of the conventional static models (additive white Gaussian noise or with time-invariant colored PSD), leading to better optimization of the implemented devices.

In this paper, a low-power second-order feed-forward capacitor-structure continuous-time $\mathrm{\Delta }\mathrm{\Sigma }$ modulator with a 4-bit asynchronous successive approximation register (SAR) quantizer is presented. Through the utilization capacitor structure in the proposed modulator, first, the summation node of the integrators’ outputs and the feed-forward signals is implemented within the second integrator to reduce power consumption by eliminating an active summing amplifier. Second, the proposed architecture can compensate for the quantizer delay without using any excess inner digital to analog converter (DAC). In this design, the modulator applies two different low-power operational amplifiers. These advantages cause the modulator to consume very low power and achieve a favorable figure of merit (FOM) value. In fact, in this paper, the combination of the previously reported methods and designs and doing required reforms has led to a new design with better performance, especially in power reduction. The designed modulator which is simulated using 0.18$\mu$m CMOS technology achieves 95.98dB peak signal-to-noise and distortion (SNDR) for 10KHz signal bandwidth and dissipates 44$\mu$w while its FOM is obtained about 43 fJ/conv.-step.

Rectilinear Steiner Tree (RST) construction is a fundamental problem in very large scale integration (VLSI) physical design. Its applications include placement and routing in VLSI physical design automation (PDA) where wire length and timing estimations for signal nets are obtained. In this paper, a pseudo-Boolean satisfiability (PB-SAT)-based approach is presented to solve rectilinear Steiner tree problem. But large nets are a bottleneck for any SAT-based approach. Hence, to deal with large nets, a region-partitioning-based algorithm is taken into consideration, which eventually achieves a reasonable running time. Furthermore, a clustering-based approach is also explored to improve the partitioning of nets by identifying clusters and then applying a heuristic-based approach to get the minimum wire length for each set of the clusters. Experimental results obtained by these techniques show that the proposed algorithm can solve the RST problem very effectively even on large circuits and it outperforms the widely used RST algorithm FLUTE with 3$\times$to 9$\times$speedups.

Reduction in the overall power devices such as power semi-conductor switches, gate drivers with the associated circuits and DC voltage sources reduces the size, cost, complexity in addition with enhancing the overall performance of the inverter. This paper presents a new and generalized multilevel inverter topology with reduced number of power components. To identify the significance of proposed inverter, the generalized formulae for all the parameters are calculated and a comprehensive comparison of different performance parameters are presented in tabular as well as in graphical form. Multicarrier pulse width modulation strategy is adopted for generating the switching pulses. Simulation of the proposed MLI topology for the 9-level and 17-level inverter have been performed in MATLAB/Simulink and the corresponding experimental results are incorporated for one unit and two units, respectively, experiments are carried out at RL load. Nevertheless, level per switch Ratio (L/S) is introduced and compared with some of the new discussed MLI topologies. Moreover, the switching and the conduction losses of the inverter are also calculated and incorporated in this paper.

In this paper, a wideband low-noise amplifier (LNA) is designed based on the resistive feedback topology with a TSMC 0.18$\mu$m standard RF CMOS process. Bandwidth expansion is provided by the second-order Chebyshev filter. The noise figure (NF) increases at high frequency because of the source parasitic capacitors of the cascode transistor; so, noise cancelling technique is applied to the cascode transistor of the proposed LNA. Bias conditions and sizes of the transistors are optimized to cancel the nonlinear transconductance ($g_m^{\prime },g_m^{\prime }$). With this modified technique, low noise figure, high linearity and improved input and output matching can be attained for 3.1–10.6GHz frequency band. Post-layout simulation result of the proposed LNA shows the maximum power gain of 17dB at 5.5GHz frequency, NF of lower than 4.5dB over the whole band of 3.1–10.6GHz, maximum IIP₂ of $+$28dBm and IIP₃ of $+$7.5dBm, while dissipating 9mW (with buffer) from a 1.8 V supply voltage. It occupies $773.3\mu \mathrm{\text{m}}\times 676\mu$m silicon die area.

In this work, a high-performance voltage and current output instrumentation amplifier circuit is proposed. The proposed circuit also has voltage-mode (VM) and transadmittance-mode (TAM) outputs at a time. It employs a single current backward transconductance amplifier (CBTA) and a grounded resistor. It has the advantage of having low input and high output impedances which makes it easy for cascadability. The presented circuit has electronically tunable property due to the bias current of the CBTA. The validity of the proposed circuit is demonstrated by PSPICE simulations using a 0.18$\mu$m CMOS process with $\pm 0.9$V supply voltage. Simulation results show that the proposed circuit has a high common mode rejection ratio (CMRR), wide bandwidth, low offset and high gain properties.

This paper describes a technique to detect blood cell levels based on the time-period modulation of a relaxation oscillator loaded with an Inter-Digitated Capacitor (IDC). A digital readout circuit has been proposed to measure the time-period difference between the two oscillators loaded with samples of healthy and (potentially) unhealthy blood. A prototype circuit was designed in 65-nm CMOS technology and post-layout simulations show 15.25-aF sensitivity. The total circuit occupies 2,184-$\mu$m² silicon area and consumes 216$\mu$A from a 1-V power supply.

In recent times, instead of three-phase induction motors (IM), multi-phase motors have been used in several applications, due to numerous advantages that they offer. Elimination of mechanical position or speed sensors allures for adjustable speed drives of IM. It leads to cost reduction, lesser maintenance and increased reliability of the motor drive. To eliminate the speed sensor, the rotor speed is estimated from measured stator currents and voltages at motor terminals. This paper proposes a scheme based on speed estimation method using Model Reference Adaptive System (MRAS) in conjunction with Adaptive Fuzzy Knowledge Based Controller (AFKBC) to improve the performance of a sensorless Indirect Rotor Field Oriented Control (IRFOC) of six-phase IM drive. AFKBC allows to operate at various operating conditions. A fitness function is defined for Queen Bee-based Genetic Algorithm (QBGA) to tune the scaling factor of AFKBC which improves the transient and steady state performances. The performance of the proposed scheme is evaluated by simulation on Matlab/Simulink package. The results of the proposed scheme are compared with conventional PI-based speed controller of the drive system. The proposed controller scheme improves the performance of the drive system at various operating conditions. The estimated speed algorithm gives good correlation between estimated and actual motor speed. The simulation results also illustrate that proposed scheme is robust and suitable for high performances six-phase IM drive.

The natural calamity and physical malfunction in the overhead transmission line cause bad impact on the networks such as mechanical failures, power losses, reduction of line capacity, and voltage drop. These adverse impacts can be reduced by implementing proper monitoring systems. Wireless sensor network is an apt mechanism to monitor the overhead transmission network because of its physical configuration. This paper portrays the communication between wireless sensor networks and central data processing station. Cellular communication can directly transmit information through an assisted cellular module (CM) based on the probability of cellular coverage. In this paper, one of the modern optimization techniques, i.e., artificial bee colony algorithm, is used to study the problem of CM placement of cellular communication. By using this algorithm, the optimal number and location of the CMs for a test system varied from 10 to 100 are determined. A novel optimal link path scheme is proposed to check the condition of the required quality of services of both cellular/ZigBee users. The attained results show that the methodology is best suited to acquire low cost solution for the cellular module placement problem.

Unified Power Quality Conditioner (UPQC) with a modified Power Angle Control (PAC) scheme is presented for effective interconnection of renewable energy system into the grid. The UPQC consists of both shunt and series Active Power Filters (APFs). The shunt and series APF is one of the most effective custom power devices, which provides compensation for current and voltage-based disturbances, respectively. The shunt APF supplies active power to the load from the Distributed Generation (DG) in addition to reactive power demand supplied by it. Because of this functionality, the Volt–Ampere (VA) burden increases along with the rating of the shunt inverter. The PAC scheme aims to effective utilization of series and shunt APFs through sharing of reactive power to reduce VA burden on shunt APF. The PAC scheme is based on Synchronous Reference Frame (SRF) theory, which has simple computations, is robust and uses existing measurements of Solar Photovoltaic (SPV)-integrated UPQC. The performance of the proposed SPV-integrated UPQC is verified with the manifestation of nonlinear loads and reactive burdens with the SPV power generating system. The dynamic performance of the PV-UPQC is verified under the grid disturbances such as voltage sag, swell, varying load and change in solar irradiation. The effectiveness of the proposed control scheme is evaluated through the digital simulation and hardware experimental prototype model.

This paper introduces a novel approach of transconductance boosting for current differencing transconductance amplifier (CDTA). Generally, the variation in the transconductance is achieved by changing the bias current and/or by increasing the aspect ratios of differential pair MOSFETs. These techniques of transconductance variations suffer from several serious drawbacks which include higher power dissipation, limited range of transconductance gain and lower input/output swing. The proposed approach of transconductance boosting overcomes these drawbacks at certain extent and also provides a high value of transconductance gain with acceptable range of bandwidth and power dissipation. It includes two different techniques to make it more effective for transconductance boosting. In the first technique, common source amplifiers have been used between gate and source terminals of the differential pair MOSFETs whereas in the second technique the concept of partial positive feedback is utilized. Using this approach, a new structure of CDTA namely cross-coupled common source current differencing transconductance amplifier I (CCCS-CDTA I) is proposed. To further improve the transconductance gain of CCCS-CDTA I, another structure CCCS-CDTA II is also proposed, in which the differential pair MOSFETs are replaced by two networks of “n” parallel MOSFETs having same aspect ratios. The proposed CCCS-CDTAs are simulated in Mentor Graphics Eldo simulator using TSMC 0.18$\mu$m process parameters. To confirm the performance of CCCS-CDTA II, physical layout and post-layout simulation results have been presented using Mentor Graphics Calibre tool. The advantages of proposed CCCS-CDTAs have also been discussed by realizing KHN filters and oscillators.

Power quality (PQ) issue is referred to as any problem that exposes in the voltage and current or in frequency value that causes a malfunction of protection devices or maloperation of the system. The improvement of the PQ is important at the load side when the production processes get more complicated and require a bigger liability level. An Elephant Herding Optimization (EHO) algorithm is presented for improving the PQ and reducing the harmonic distortion using the Static Switched Filter Compensation (SSFC) in Photovoltaic (PV) interconnected wind energy conversion system (WECS). The novelty of the proposed system is enhancing the performance of the grid-connected hybrid energy system such as stabilizing the voltage, reducing the power loss and mitigating the harmonic distortion using the SSFC. Here, the proposed controller is used to optimize the control pulses for SSFC. The SSFC and voltage-source converters with smart dynamic controllers are emerging as stabilization and power filtering equipment to improve the PQ. The proposed method has implemented in MATLAB/Simulink platform and their performances are evaluated and contrasted with the existing technologies such as Bat algorithm (BA) and Firefly algorithm (FA) techniques.