Journal of Circuits, Systems and Computers

In this work, the design of the diminished-1 modulo $2^n+1$ adders, subtractors and adders/subtractors are examined. Some of the existing modulo $2^n+1$ adders, subtractors and adder/subtractors are redesigned and improved. Compared to other existing implementations, the proposed subtractor and adder/subtractors offer reduced area complexity and lower power consumption, while operating at the same speed. All the considered architectures are modified parallel-prefix adders with fast input carry processing. The totally parallel-prefix and carry look ahead implementation of the proposed arithmetic units are also discussed.

Data stability, write ability and leakage power are major concerns in submicron static random access memory (SRAM) cell design. This paper presents an 11T SRAM cell with differential write and single-ended read. Proposed cell offers improved write ability by interrupting its ground connection during write operation. Separate read buffer provides disturb-free read operation. Characteristics are obtained from HSPICE simulation using 32nm high-performance predictive technology model. Simulation results show that the proposed cell achieves 4.5$\times$ and 1.06$\times$ higher read static noise margin (RSNM) as compared to conventional 6T (C6T) and PNN-based 10T cells, respectively, at 0.4V. Write static noise margin (WSNM) of the proposed design is 1.65$\times$, 1.71$\times$ and 1.77$\times$ larger as compared to those of C6T, PPN-based 10T and PNN-based 10T cells, respectively, at 0.4V. Write “1” delay of the proposed cell is 0.108$\times$ and 0.81$\times$ as those of PPN10T and PNN10T cells, respectively. Proposed circuit consumes 1.40$\times$ lesser read power as compared to PPN10T cell at 0.4V. Leakage power of the proposed cell is 0.35$\times$ of C6T cell at 0.4V. Proposed 11T cell occupies 1.65$\times$ larger area as compared to that of conventional 6T.

Autoconfiguration in mobile ad hoc network (MANET) is a challenging task to be accomplished in hostile environment. Moreover, a mobile node in MANET is usually configured with a unique IP address for providing better communication and to connect it with an IP network. Essentially, the nodes in wired networks are autoconfigured using a commonly known Dynamic Host Configuration Protocol (DHCP) server. However, MANET exhibits the intrinsic characteristics (i.e., distributed, dynamic and multi-hop) in nature; hence, it is hard to adopt DHCP server for autoconfiguration of nodes in MANET without applying significant modifications in auto-configuration scheme. This paper proposes an efficient IPV6 Duplicate address Elimination Autoconfiguration protocol for MANETs (IDEAM) which comprises the member and the cluster head (CH) nodes organized in a hierarchical fashion. Further, the proposed protocol considers the global connectivity exhibiting reduced communication overhead among the nodes. Initially, our proposed auto-configuration protocol encourages the Duplicate Address Detection (DAD) operation by selecting a controller node from the prefixed group members using a joining node in the network. In other words, the DAD operation is performed perfectly by a selected controller node on behalf of the new joining node. Thus, our proposed protocol becomes more effective and behaves better in the minimization of overhead by considerably eliminating the DAD messages broadcast in the network. Also, we imposed a new Flower pollination based gray wolf optimization (FPGWO) algorithm for selecting an optimal header among the group members by considering various node parameters (i.e., node location, resources and node density) to avoid unnecessary broadcasting of additional weight messages about each node in the network. The simulation results proved the efficiency of our proposed protocol in terms of scalability and in the minimization of overhead. Also, an effectual method provided by our proposed approach enhances the activity of marginal nodes over the group for healing the network that degrades its performance followed by the splitting and merging operation.

This paper proposes a new single-input dual-output [SIDO] soft-switched resonant full-bridge converter, which has asymmetrical structures for the isolated multiple outputs. The proposed structure is capable of supplying different loads having dissimilar voltage-current characteristics and independent of each other. This converter features wide range of zero current switching (ZCS) turn-off and automatic load-voltage regulation. In automatic load-voltage regulation, converter maintains constant voltage without the need of change in frequency or duty ratio during load change. First, the modes of converter operation are explained and then design of key parameters have been outlined. A laboratory prototype for 380V, 500W as main output and 24V, 50W as auxiliary output for an input voltage range of 40–50V was built-up and tested. Experimental results confirm the viability of voltage regulation, ZCS and power efficiency of the proposed converter.

The implementation of Wireless Sensor Networks (WSNs) is a challenging task due to their intrinsic characteristics, e.g., energy limitations and unreliable wireless links. Considering this, we have developed the Disjoint path And Clustering Algorithm (DACA) that combines topology control and self-healing mechanisms to increase the network lifetime with minimum loss of coverage. Initially, DACA constructs a tree that includes all nodes of the network by using the Collection Tree Protocol (CTP). This tree is an initial communication backbone through which DACA centralizes the information. Then, DACA builds a set of spatial clusters using Kmeans and selects the Cluster Heads (CHs) using Particle Swarm Optimization (PSO) and a multi-objective optimization (MOO) function. Subsequently, DACA reconstructs the tree using only the CHs. In this way, DACA reduces the number of active nodes in the network and saves energy. Finally, DACA finds disjoint paths on the reconstructed tree by executing the N-to-1 multipath discovery protocol. By doing so, the network can overcome communications failures with a low control message overhead. The simulations on Castalia show that DACA considerably extends the network lifetime by having a set of inactive nodes and disjoint paths that support the communication when active nodes die. Besides, DACA still maintains a good coverage of the area of interest despite the inactive nodes. Additionally, we evaluate the shape of the tree (i.e., the average number of hops) and the risk of connection loss of the network.

The designs using ternary logic exploit its logarithmic reduction in the number of qudits compared with the binary circuits. In this paper, we propose quantum ternary multiplication gate. We term it as QTMG. Then we present the symbol and the realization of QTMG. Researchers will be able to use this gate as well as its symbol and realizations in their future studies. We also present a new realization of ternary Toffoli gate in specific state. Moreover, in this paper, we propose 1-qutrit multiplier circuit. The symbol and the realization of the proposed 1-qutrit multiplier circuit are also provided. Afterward, we proposed ternary partial products generation circuit (TPPG) and summation network circuit in order to design quantum ternary 2-qutrit multiplier circuit. Overall, the proposed design of QTMG in this paper is suggested for the first time. In addition, the proposed realization of ternary Toffoli gate, TPPG, summation network and 2-qutrit multiplier circuits are compared with the existing designs and the improvements are reported. The proposed gate and circuits are realized using macro-level ternary gates which are built on the top of the ion-trap realizable 1-qutrit gates and 2-qutrit Muthukrishnan–Stroud gates.

In this paper, a new transformerless buck-boost converter is presented. The voltage gain of the converter is higher than the classic boost converter, classic buck-boost converter, CUK and SEPIC converters. The proposed converter advantage is buck-boost capability. The proposed converter topology is simple; therefore, the converter control is simple. The converter has one main switch. Hence, the switch with low switching and conduction losses can be used. The stress of the main switch is low; therefore, switch with low on-state resistance can be selected. The principles of the converter and mathematic analyses are presented. The validity of the accuracy of calculations is verified by the experimental results.

A 4-bit flash ADC utilizing the advantage of digital-based differential voltage comparator is presented in this paper. This circuit has an advantage of digital circuit concept and can be easily migrated to lower technologies. Also, the digital circuits are less sensitive to the noise and device mismatches can be synthesized and auto place and route (P&R) using EDA tools. The design of the proposed comparator is based on the standard cells implementation. As the proof of concept this comparator is implemented on Xilinx Basys-3 Artix-7 FPGA kit. The prototype of complete 4-bit Flash ADC is designed in 180nm CMOS technology with 1.8V supply voltage. The measured values of ENOB, SNDR, SNR and SFDR are 3.6, 23.43dB, 25.2dB and 30.1dB, respectively at 33.20MHz input frequency and 200MHz clock frequency. The total power consumed by the 4-bit flash ADC is 2.14mW. The calculated value of DNL and INL is $<0.4$ LSB and $<0.5$ LSB respectively.

In most systems, a smart functionality is enabled through an essential vital service such as detecting anomalies from complex, large-scale and dynamic data. However, ensuring the privacy and security for the cloud data is the most crucial and challenging task in the present world. Moreover, it is important to safeguard the security of sensitive data and its privacy from unauthorized parties who are trying to access the data. Therefore, to accomplish this task, several encryption, decryption and key generation mechanisms were introduced in the existing works for privacy preserving in cloud platform. But, there still remain open issues such as increased communication overhead, reduced security and increased time consumption. Also, these existing works followed the symmetric key cryptographic mechanism for privacy preservation of data; hence, a single secret key is shared by several users for accessing the original data. Due to this fact, a high security risk arises and it allows unauthorized parties to access the data. Thus, this work introduces a cloud-based privacy preserving model for offering a scalable and reliable anomaly detection service for sensor data through holding the benefits of cloud resources. Also, this paper aims to impose a newly developed Elliptic Curve Cryptography-based Collective Decision Optimization (ECDO) approach over the proposed framework for improving the privacy and security of the data. Furthermore, to perform the data clustering computation we used the Gaussian kernel fuzzy $c$-means clustering (GKFCM) algorithm within the cloud platform, especially for data partitioning and to classify the anomalies. Thus, the computational difficulties are limited by adopting this suitable privacy preserving model which collaborates a private server and a set of public servers through a cloud data center. Moreover, on encrypted data the granular anomaly detection operations are performed by the virtual nodes executed over public servers. Experimental validation was performed on four datasets resulting from Intel Labs publicly available sensor data. The experimental outcomes demonstrate the ability of the proposed framework in providing high anomaly detection accuracy without any degradation in data privacy.

The Linux Unified Key Setup (LUKS) is the standard key management scheme for the full disk encryption solution implemented in Linux-based operating systems. It is composed of PBKDF2, an anti-forensic splitter, and a cipher. In this paper, a new FPGA-based high-throughput and pipelined implementation of LUKS is presented. We design a four-stage pipelined SHA-1 module without the multiplexers between piecewise function and a total eight-stage pipelined PBKDF2 by reusing two hash results. Besides, we implement ST box-based AES decipher with BRAM resources, which improves the performance and leaves most of the slice resources to PBKDF2 architecture. By using the above techniques, we instantiate a high throughput LUKS co-processor in a Xilinx Zynq 7030 FPGA. Compared to the previous work of implementation of LUKS PBKDF2 with AES on FPGA, our design shows better improvement of the speed and efficiency by 16 times and 8 times, respectively. Our speed of LUKS key recovery is even faster than Nvidia GPU GTX480.

This paper presents the design and implementation of an RF energy harvester system at 5.8GHz for low-power wireless transmission applications. The potential application of the proposed system is to wirelessly power sensor nodes. First, a design methodology of the rectifier based on a theoretical approach is presented. The simulation results show an excellent correlation with the theoretical ones, proving the accuracy of the proposed design methodology. A prototype is fabricated and the simulation results are validated by the measurements. Then, the rectenna is combined to a commercial power management circuit and a load which emulates the behavior of a sensor. The power management circuit boosts and regulates the output DC voltage as well as stores the collected energy into a capacitor. Finally, the complete system is experimentally tested and excellent performances are demonstrated. The efficiency of the RF energy harvester is 24% at $-$10dBm input power and 47% at $-$5dBm input power which are the highest reported measured efficiencies at this frequency and at those power levels. The complete rectenna system is able to harvest 4.62mJ in 40 s and 192s for $-$6dBm and $-$10dBm input power, respectively allowing us to power wirelessly low-power electronic devices.

An active quasi-circulator (AQC) integrated circuit is designed and fabricated in a 0.18-$\mu$m CMOS process. The proposed design is based on a parallel combination of a common-source (CS) stage and a combined common-drain (CD) and common-gate (CG) topology. Scattering matrix of the core AQC circuit is derived considering MOSFET’s secondary effects, particularly the body effect as well as output loading effects. Measurements of the quasi-circulator reveal an insertion loss of $6.8\pm 0.5$ dB between transmitter-to-antenna ports ($|S_{21}|$) and of $7.4\pm 0.5$ dB between antenna-to-receiver ports ($|S_{32}|$), within a frequency band of 2.2–4.6 GHz. The isolation between the transmitter and the receiver ports ($|S_{31}|$) is better than 24 dB with a maximum value of 29.5dB @ 3.6GHz. The power dissipation of the proposed AQC is 40mW and it covers an active chip area of 0.677mm².

In this paper, a new active element namely Dual-X current conveyor differential input transconductance amplifier (DXCCDITA) is proposed. The DXCCDITA is utilized in designing four minimum component fully cascadable all pass filter (APF) structures. The designed all pass filters require only single active element and one/two passive elements for realization thus making them a minimum component implementation. Two among the four presented all pass structures require only a single capacitor for implementation. A scheme for realizing nth order all pass filter is also suggested and a fourth order voltage mode (VM) filter is developed from the proposed scheme. The effect of non-idealities on the proposed all pass filters is also studied. A simple oscillator is also developed using one of the all pass filter structure. The oscillator required only one DXCCDITA, two capacitors and one resistor for implementation. The DXCCDITA is implemented in 0.35$\mu$m TSMC CMOS technology parameters and tested in Tanner EDA. Sufficient numbers of simulations are provided to establish the functionality of all pass structures. The experimental results using commercially available integrated circuits (ICs) are also provided.

Decision diagrams are a data structure suitable for reversible circuit synthesis. Functional decision diagrams (FDDs) are particularly convenient in synthesis with Toffoli gates, since the functional expressions for decomposition rules used in them are similar to the functional expressions of Toffoli gates. The main drawback of reversible circuit synthesis based on decision diagrams is the usually large number of ancilla lines. This paper presents two methods for the reduction of the number of ancilla lines in reversible circuits derived from FDDs by selecting the order of implementation of nodes. In the first method, nodes are implemented by levels, starting from the bottom level to the top. The method uses appropriately defined level dependency matrices for choosing the optimal order of implementation of nodes at the same level. In this way, the optimization is performed level by level.

The second method uses a diagram dependency matrix expressing mutual dependencies among all the nodes in the diagram. This method is computationally more demanding than the first method, but the reductions of both the number of lines and the Quantum cost of the circuits are larger.

Designing of Complementary Metal Oxide Semiconductor (CMOS) technology based VLSI circuits in deep submicron range includes many challenges like tremendous increase of leakage power. Design is also easily affected by process variation. The Carbon NanoTube Field Effect Transistor (CNTFET) is an alternative for Metal Oxide Semiconductor Field Effect Transistor (MOSFET) for nanoscale range VLSI circuits design. CNTFET offers best performance than MOSFET. It has high stability and consumes least power. Static Random Access Memory (SRAM) cells play a vital role in cache memory in most of the electronic circuits. In this paper, we have proposed a high stable and low power CNTFET based 8Transistor (8T) SRAM cell. The performance of proposed 8T SRAM cells for nominal chiral value (all CNTFET with $m=19$, $n=0$) and Dual chiral value (NCNTFET with $m=19$, $n=0$ and PCNTFET $m=16$, $n=0$) is compared with that of conventional 6T and 8T cells. From the simulation results, it is noted that the proposed structure consumes less power than conventional 6T and 8T cells during read/write operations and gives higher stability during write and hold modes. It consumes higher power than conventional 6T and 8T cells during hold mode and provides lower stability in read mode due to direct contact of bit lines with storage nodes. A comparative analysis of proposed and conventional 8T MOSFET SRAM has been done and the SRAM parameters are tabulated. The simulation is carried out using Stanford University 32nm CNTFET model in HSPICE simulation tool.

This paper proposes a shunt Active Power Filter (APF), supported by Solar Photovoltaic (SPV) system for a grid-connected application that improves power quality. The reference signal for the shunt APF is obtained from the adaptive Proportional Integrative Derivatives (PID), based on an algorithm of Least Mean Eighth (LME) with Unit Vector Template (UVT). The LME algorithm distinguishes the basic weight sections from load currents and estimates the three phase reference source current. These reference currents are used to generate a gate signal for the shunt APF. The DC-link voltage regulator is used to keep the constant DC-link voltage of the shunt APF with an APID controller. To reduce present distortions of electric power distribution systems, a design of a suitable controller is conducted using an intelligent computational technique for predicting the right reference signals. The SPV scheme is designed to obtain the highest energy output from the SPV panel with the maximum power point tracking algorithm (MPPT) scheme and is connected to the power grid. For long-term harmonic mitigation, the SPV system continuously maintains the DC-link of the shunt APF. Mathematically, the presented current reference signal generation scheme is examined and digital simulation outcomes are displayed under distinct steady and dynamic state conditions. Lastly, the complete scheme is validated by using the hardware prototype.

In Low Earth Orbit (LEO) satellite networks, it is a challenge to allocate the limited resources to meet the needs of different calls. In this paper, a dynamic channel reservation strategy based on priorities of multi-traffic and multi-user in LEO satellite networks is proposed. The dynamic admission threshold reserved for different calls is the key of this strategy. Firstly, the traffic prediction model based on LEO satellite mobility is established. Then the channel allocation model is built on the Markov process. Finally, the reserved admission thresholds are dynamically changed according to the predicted traffic. And the calculation of the admission thresholds is solved by the genetic algorithm. The simulation results show that the proposed strategy not only meets the needs of calls of different type traffic and different level users, but also improves the overall quality of service in LEO satellite networks.

The dual-slope integral analog-to-digital converter is widely used in low-speed, high-precision measurement owing to its high precision and strong resistance on crosstalk interference. To meet the requirements of higher accuracy and faster measurement, the integral sensitivity and conversion speed of the dual-slope integral analog-to-digital converter must be improved. Therefore, based on fractional-order calculus, we propose a fractional-order dual-slope integral analog-to-digital converter. First, constant-current charging curves were provided to explain the source of the idea of the fractional-order dual-slope integral analog-to-digital converter. Then, the working principle of the fractional-order dual-slope integral analog-to-digital converter is described in detail. The calculation formula of analog-to-digital conversion is derived and analyzed. Moreover, the relationship of the voltage-measurement error with the operation-order error of the fractor and the reference voltage error is theoretically derived. Furthermore, we theoretically analyze the resistance of the proposed analog-to-digital converter to crosstalk interference, as well as the requirements for the first fractional integral time when crosstalk interference is suppressed. Specifically, we prove that the proposed analog-to-digital converter has a higher sensitivity and conversion speed than the classical converter, and we provide a quantitative calculation formula.