Journal of Circuits, Systems and Computers

Impedance source-based multilevel inverters are becoming popular for emerging power generation technologies such as fuel cells, photovoltaic, and wind turbines. It is one of the most promising power electronic interfaces for single stage DC/AC conversion with inherent buck-boost capability. Therefore, in this paper, an extensive review of emerging impedance source-based multilevel inverter (Z-MLI) topologies is presented. These topologies are developed by the combination of impedance source network and multilevel inverter (MLI) with the merits of high voltage gain, enhanced reliability due to shoot-through immunity, improved input voltage regulation, reduced filter size, and better quality of supply. Most of the recent Z-MLI topologies are based on quasi-Z-source network which operates with continuous input current. In order to identify a suitable topology, an exhaustive comparison is made with various configurations of Z-MLIs in terms of component count, boost gain, switching stress, and control complexity.

Modern decananometer-sized MOS transistors tend to exhibit high rates of failure, underscoring the need for accurately estimating the unreliabilities of circuits built from such transistors. This paper presents a methodology for unreliability calculation that extends from individual transistors to complete logic circuits. As a logic cell’s or logic circuit’s unreliability is highly dependent on its transistors’ drain–source and gate–source voltages, SPICE simulations are used to determine the voltages for the individual transistors. The voltage measurements are then utilized by the mathematical equations to predict the unreliabilities with high accuracy. A scalable framework based on the proposed methodology has been successfully implemented. The framework has been validated using ISCAS85 benchmark circuits.

Designing energy-efficient scheduling algorithms on heterogeneous distributed systems is increasingly becoming the focus of research. State-of-the-art works have studied scheduling by combining dynamic voltage and frequency scaling (DVFS) technology and turning off the appropriate processors to reduce dynamic and static energy consumptions. However, the methods for turning off processors are ineffective. In this study, we propose a novel method to assign priorities to processors for facilitating effective selection of turned-on processors to decrease static energy consumption. An energy-efficient scheduling algorithm based on bisection (ESAB) is proposed on this basis, and this algorithm directly turns on the most energy-efficient processors depending on the idea of bisection to reduce static energy consumption while dynamic energy consumption is decreased by using DVFS technology. Experiments are performed on fast Fourier transform, Gaussian elimination, and randomly generated parallel applications. Results show that our ESAB algorithm makes a better trade-off between reducing energy consumption and low computation time of task assignment (CTTA) than existing algorithms under different scale conditions, deadline constraints, and degrees of parallelism and heterogeneity.

The applications of wireless sensor network (WSN) are growing very rapidly, so utilizing the energy in an efficient manner is a challenging task as the battery life of nodes in WSN is very limited. For enhancing the lifetime of the network, various clustering protocols have been proposed earlier. In this paper, a clustering protocol named Energy Efficient Clusterhead Selection Scheme (ECSS) is proposed. The proposed ECSS protocol focusses on selecting an energy-efficient cluster head (CH), which helps in enhancing the overall lifetime and performance of the network. The proposed ECSS protocol uses the energy levels of nodes for the CH selection process. The proposed protocol is designed for the heterogeneous environment and it aims in minimizing the energy usage in the network and thereby improving the lifespan of the network. To measure the performance of the proposed ECSS protocol, the comparison is performed with the various existing protocols using MATLAB simulator. The results of simulation show that the proposed ECSS protocol has enhanced the network lifespan, throughput, and energy usage of the network as contrasted to the existing protocols.

The evolution of the wireless sensor network (WSN) in recent years has reached its greatest heights and applications are increasing day by day, one such application is Smart Emergency Monitoring Systems (SMESs) which is in vision of implementation in every urban and rural areas. The implementation of WSN architecture in the Smart Monitoring Systems needs an intelligent scheduling mechanism that efficiently handles the high traffic load as well as the emergency traffic load without sacrificing the energy efficiency of the network. However, the traditional scheduling algorithms such as First Come First Served (FCFS), Round Robin, and Shortest Job First (SJF) cannot meet the requirements of high traffic load in SMESs. To address these shortcomings, this paper presents Emergency Adaptive Medium Access Control protocol (EA-MAC), a fuzzy priority scheduling based Quality-of-service (QoS)-aware medium access control (MAC) protocol for hierarchical WSNs. EA-MAC protocol employs the most powerful fuzzy logics to schedule the sensor nodes with both normal and emergency traffic load without any data congestion, and packet loss and maintaining the better QoS which is considered to be more important in SMESs applications. Moreover, a novel rank-based clustering mechanism in EA-MAC protocol prolongs the network lifetime by minimizing the distance between the Cluster Head (CH) and the Base Station (BS). Both analytical and simulation models demonstrate the superiority of the EA-MAC protocol in terms of energy consumption, transmission delay and data throughput when compared with the existing Time Division Multiple Access (TDMA) based MAC protocols such as LEACH protocol and Cluster Head Election Mechanism-Based On Fuzzy Logic (CHEF) protocol.

In this paper, a 11-T static random-access memory (SRAM) cell has been examined that shows a fair reduction in read power dissipation while upholding the stability and moderate performance. In the presented work, parametric variability analysis of various design metrices such as signal to noise margin, read current and read power of the Proposed 11T cell are presented and compared with few considered topologies. The Proposed cell offers single ended write operation and differential read operation. The improvement in read signal to noise margin and write signal to noise margin with respect to conventional 6T SRAM is 10.63% and 33.09%, respectively even when the write operation is single ended. Mean hold static noise margin of the cell for 3000 samples is $1.75\times$ times higher than considered D2p11T cell. Sensitivity analysis of data retention voltage (DRV) with respect to temperature variations is also investigated and compared with considered topologies. DRV variation with temperature is least in FF process corner. In comparison to conventional 6T SRAM cell, the write and read delay of Proposed 11T cell gets improved by $2.55\times$ and 1.64%, respectively. Proposed 11T topology consumes least read energy in comparison with considered topologies. In comparison with another considered 11T topology, i.e., D2p11T cell, Proposed cell consumes 13.11% lesser area. Process variation tolerance with Monte Carlo simulation for read current and read power has been investigated using Cadence virtuoso tool with GPDK 45-nm technology.

In this paper, the design of a fuzzy rule-based MDPSM controlled buck converter is analyzed. Power factor improvement and harmonic minimization for the buck converter connected through the variable load with a fuzzy rule are discussed and simulated. The MDPSM controlled converter is supplied with 230V and reaches 15V as output. The converter output, always connected with nonlinear loads, causes less power factor with more harmonics and gives less power quality. Active PFC with a fuzzy-based voltage controlled power factor controller is designed to reduce total harmonics and to raise the power factor value equal to unity. The fuzzy-based MDPSM controller was designed using MATLAB Simulink. Controller output waveforms are examined and analyzed with other controller performances. The converter is rated with 2mA, 0.5mH and 212$\mu$F values with output power 48W. The converter is tested for different resistive loads and inductive loads.

Effective resistance to intellectual property (IP) piracy, overproduction and reverse engineering are becoming more and more necessary in the integrated circuit (IC) supply chain. To protect the hardware, the obfuscation methodology hides the original function by adding a large number of redundant states. However, existing hardware obfuscation approaches have hardware overhead and efficiency of obfuscation limitations. This paper proposed a novel methodology for IP security using the minimum spanning tree finite state machine (MST-FSM) obfuscation. In the minimum spanning tree (MST) algorithm, the Hamming distance defines the cost of obfuscated states. The Kruskal algorithm optimizes the connection relationship of obfuscated states by computing the Hamming distance of the MST-FSM. The proposed MST-FSM is automatically generated and embedded in the hardware IP with the self-building program. Finally, the MST-FSM is applied on the itc99 benchmark circuits and encryption standard IP cores. Compared with other state-of-the-arts, the obfuscation potency is improved by 3.57%, and the average hardware cost is decreased by about 6.01%.

Reversible logic and Quantum dot cellular automata are the prospective pillars of quantum computing. These paradigms can potentially reduce the size and power of the future chips while simultaneously maintaining the high speed. RAM cell is a crucial component of computing devices. Design of a RAM cell using a blend of reversible logic and QCA technology will surpass the limitations of conventional RAM structure. This motivates us to explore the design of a RAM cell using reversible logic in QCA framework. The performance of a reversible circuit can be improved by utilizing a resilient reversible gate. This paper presents the design of QCA-based reversible RAM cell using an efficient, fault-tolerant and low power reversible gate. Initially, a novel reversible gate is proposed and implemented in QCA. The QCA layout of the proposed reversible gate is designed using a unique multiplexer circuit. Further, a comprehensive analysis of the gate is carried out for standard Boolean functions, cost function and power dissipation and it has been found that the proposed gate is 75.43% more cost-effective and 58.54% more energy-efficient than the existing reversible gates. To prove the inherent testability of the proposed gate, its rigorous testing is carried out against various faults and the proposed gate is found to be 69.2% fault-tolerant. For all the performance parameters, the proposed gate has performed considerably better than the existing ones. Furthermore, the proposed gate is explicitly used for designing reversible D latch and RAM cell, which are crucial modules of sequential logic circuits. The proposed latch is 45.4% more cost effective than the formerly reported D latch. The design of QCA-based RAM cell using reversible logic is novel and not reported earlier in the literature.

Today’s vehicles have become increasingly complex, as consumers demand more features and better quality in their cars. Most of these new features require additional electronic control units (ECU) and software control, constantly pushing back the limits of existing architectures and design methodologies. Indeed, modern automobiles have a larger number of critical time functions distributed and running simultaneously on each ECU. Data Distribution Service (DDS) is a publish/subscribe middleware specified by the international consortium Object Management Group (OMG), which makes the information available in real time, while offering a rich range of quality of service (QoS) policies. In this paper, we propose a new methodology to integrate DDS in automotive application. We evaluate the performance of our new design by testing the fulfillment of real time QoS requirements. We also compare the performance of the vehicle application when using FlexRay and Ethernet networks. Computations prove that the use of DDS over Gigabit Ethernet (GBE) is promising in the automotive field.

In elastic clusters, the service resources (or called “resources” for short) can be dynamically scaled, thus providing opportunities to cut down the energy cost of redundant resources. Generally, taking into account the Quality of Service (QoS) of clusters, resources are carefully scaled according to specific hints which are some features of system status. However, when the Service Quality Requirement (SQR) is referred to the response time of requests, some widely used features cannot well reflect the status of the QoS. Consequently, the QoS cannot be well maintained, and the energy-saving efficiency is unsatisfactory. In this paper, we indicate that under such SQR, the outstanding hint for resource scaling is the response time of requests. Accordingly, we propose a resource scaling method which scales resources leveraging an elaborate Hint of Response time (HR). More specifically, HR is credible to foresee future QoS, and our method extracts HR by tracking and making analysis on the waiting requests in each server. Moreover, when resource scaling operation is performed, our method can estimate how many resources are suitable for current workloads with a good accuracy. Thereby, our method can timely and directly scale resources to the suitable amount, thus can significantly reduce the time delay of re-matching resources. Finally, our method can significantly promote cluster performance on both the QoS and the energy-saving efficiency.

For multi-spacecraft with actuator saturation, inertia uncertainties and external disturbances, a distributed finite-time coordinated attitude tracking control problem for the spacecraft with the communication topology containing fewer information paths is investigated. Aiming at reducing the communication path, a class of distributed finite-time state observers is designed. To speed up the convergence rate of the multiple spacecraft system, a fast nonsingular terminal sliding mode function is proposed. Moreover, an adaptive control term is proposed to suppress the impact of the external state-dependent disturbances and unknown time-varying inertia uncertainties. Further considering the actuator saturation owing to its physical limitations, a saturation function is designed. With the distributed finite-time observers, the fast nonsingular terminal sliding mode function, the adaptive update law and the saturation function, a distributed finite-time coordinated attitude tracking saturation controller is designed. Using the proposed controller, the follower can synchronize with the common leader with time-varying trajectory in finite time. Simulation results demonstrate the effectiveness of the designed controller.

Complex network reconfiguration has always been an important task in complex network research. Simple and effective complex network reconstruction methods can promote the understanding of the operation of complex systems in the real world. There are many complex systems, such as stock systems, social systems and thermal power systems. These systems generally produce correlated time series of data. Discovering the relationships among these multivariate time series is the focus of this research. This paper proposes a Spearman coefficient reconstruction network (SCRN) method based on the Spearman correlation coefficient. In the SCRN method, we select entities in the real world as the nodes of the network and determine connection weights of the network edges by calculating the Spearman correlation coefficients among nodes. In this paper, we selected a stock system and boiler equipment in a thermal power generation system to construct two complex network models. For the stock network model, we used the classic Girvan–Newman (GN) algorithm for community discovery to determine whether the proposed network topology is reasonable. For the boiler network model, we built a predictive model based on an support vector regression (SVR) model in machine learning, and we verified the rationality of the boiler model by predicting the amount of boiler steam.

Digital Cryptosystems play an inevitable part in modern-day communication. Due to the complexity involved in the execution of crypto algorithms, it is realized as modular arithmetic modules. Generally, multipliers are the most time-consuming data path elements which influence the performance of modular arithmetic implementations. In this paper, the design of a hierarchy-based parallel signed multiplier without sign extension is presented. A mathematical model of the algorithm, two VLSI architectures, namely, Carry Save Adder (CSA)-based design and Parallel Prefix-based architecture are proposed. Mathematical equations of the multiplier are verified using MATLAB tool and the architectures are coded in Verilog HDL. The functionality of the same is tested using a Zynq Field Programmable Gate Array (FPGA) (XC7Z020CLG484-1), and the synthesized results are presented. Parameters, such as area, power, delay, Power Delay Product (PDP) and Area Delay Product (ADP), are compared by synthesizing the designs in Cadence RTL compiler with 180nm, 90nm and 45nm TSMC CMOS technologies. The results show that CSA-based multiplier architecture has achieved an improved PDP performance of 20% with an optimum area compared to recent work. It also shows that the parallel prefix architecture has made a 27% improvement in speed with a better PDP. By using the proposed signed multiplier, modulo $2^n-1$ and $2^n+1$ signed arithmetic modules are implemented.

We prepared a simple program for basic electrical measurements and parameter extraction from these measurements of metal–semiconductor (MS) contacts. In this paper, we introduce a basic electrical parameter calculation software (SeCLaS-PC) for semiconductor laboratories from the temperature-dependent/independent current–voltage ($I$–$V$), capacitance– voltage ($C$–$V$) and capacitance–frequency ($C$–$f$) measurement results. SeCLaS-PC program was developed using Keysight VEE Pro (Visual Engineering Environment) software and the program has a user-friendly graphical interface. More than 50 device parameters can be easily obtained, using different methods, from the $C$–$f$, temperature-dependent $I$–$V$ and temperature-dependent $C$–$V$ measurement results for one device, with our SeCLaS-PC program.

This research paper presents a novel approach to analyze the crosstalk-induced delay of multi-layered graphene nanoribbon (MLGNR) and multi-walled carbon nanotube (MWCNT) interconnects. A multi-line driver-interconnect-load (DIL) system is employed to analyze the crosstalk-induced delay for different switching transitions. The interconnect lines of the proposed DIL are said to be operated by either a resistive or a CMOS, or a CNFET driver for different switching transitions at 32-nm technology. Using the unique CNFET driver, the victim line of the multi-level MLGNR/MWCNT-based bus system experiences a delay almost 57.25% and 31.62% lesser in comparison to a resistive driver and a CMOS interconnect driver, respectively. Additionally, the overall worst-case delays are reduced by 89.45% and 98.98% for MLGNR in comparison to an equivalent MWCNT at 100$\mu$m and 1,000$\mu$m interconnect lengths, respectively.

In this paper, an efficient method is proposed for optimal allocation and sizing of Thyristor Controlled Series Compensator (TCSC) to improve the technical and economic indices of a power network with deterministic and stochastic load models. First, the compensator allocation is done in the transmission system with the deterministic load model. After calculating the technical and economic indices of the network in the presence of a deterministic load model, the proposed method is applied to the system with a stochastic load model. The two-point estimation method is used for simulating the stochastic conditions. The indices of voltage deviation and economics of the system are optimized for selecting the optimal location and size of TCSCs. The economic index comprises loss cost, cost of the produced active power of generators and also the costs of installation, operation and maintenance of TCSCs. The multi-objective particle swarm optimization (MOPSO) is utilized to optimize the objective functions. After the multi-objective optimization, the fuzzy decision method is employed to extract one of the Pareto-optimal solutions as the best compromise one. For evaluating the proposed method, comprehensive simulations have been performed on the IEEE 39-bus network by using MATLAB/Matpower software. The simulation results clearly prove the remarkable performance of the proposed method in improving the technical and economic indices of the system.

In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach.