Journal of Circuits, Systems and Computers

In this paper, we discussed about the work done by researchers for the enhancement of performance of a multiband BPF by introducing different defected ground structure (DGS) geometries. A DGS structure on a conventional inductively coupled band pass filter is used to miniaturize the resonator. By introducing a DGS on the transversal dimension of the CPW, it enhances filter performance. The DGS cell also transforms a single band to a multiband BPF by using this structure. The design technique of the filters with the DGS can be explained at very high frequencies in GHz ranges and give very accurate simulated and measured results.

Phase Change Memory (PCM) has evolved as a promising alternative over Dynamic Random Access Memory (DRAM) in terms of cell density and leakage power. While non-volatility is a desirable feature, it gives rise to the possibility of the data being present even after the power is switched off. To secure the data, encryption is normally done by using the standard Advanced Encryption Standard (AES) algorithm. Encrypting the data results in huge number of bit-flips, which reduces the lifetime of a PCM. The proposed method increases the lifetime of PCM by reducing the number of bit-flips occurred due to the encryption of modified words only and leaving the unmodified words as they are. The generated encrypted text, which is written by using the bit-flips reversal method, reduces the number of cells involved in writing by approximately 25%. This method is implemented by using Gem5 simulator and is evaluated with splash2 benchmark suite. It is observed that the proposed method improves the lifetime of a PCM memory by 15% without consuming extra power.

A power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to the previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65nm CMOS technology. It results in 81dB voltage gain, which is 21dB higher than the existing gain-boosting technique. The proposed op-amp works with as low a power supply as 0.8V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing gain below a 1.1V supply. The circuit draws a total static current of 295$\mu$A and occupies 5000$\mu$m² of silicon area.

This study describes a novel bidirectional current shunt monitor (CSM) circuit operating at both positive and negative common-mode (CM) voltages. The proposed CSM circuit mainly consists of two comparators, three error amplifiers, several current-mirror transistors and a few resistors. One comparator is used to detect current flowing direction, and the other one is utilized to ensure good operation of CSM circuit with both positive and negative CM voltages. The proposed CSM circuit has been implemented in SMIC 0.18$\mu$m standard CMOS process and its performances have been verified by simulations. The simulated results show that the proposed CSM circuit, at a supply voltage of 5V and with an input CM voltage range from $-4$ to 4V, can sense a voltage difference of 4–40mV and keep a constant scaled gain of 100V/V. The gain error is less than 0.65% and the common-mode rejection ratio (CMRR) is higher than 130dB at 1kHz. Simulation results show that the output voltage of CSM circuit varies linearly with the CSM input sense voltage.

In non-isolated bidirectional DC-DC converters (NIBIDC), voltage output of buck/boost mode is incongruous at lower and higher end due to the existing gain. In this paper, a novel NIBIDC is designed in such a way that it enhances the gain in both buck and boost mode of operation. The proposed NIBIDC is employed with four power switches (MOSFET) with an anti-parallel diode embodied, four inductors and three capacitors used as passive elements. The current flow in parallel connected inductor improves the circuit competence. Voltage gain of NIBIDC in buck operation is lower than conventional cascaded bidirectional buck/boost converter (CCBBC) whereas the voltage gain is higher than CCBBC in boost mode. The switching stress is same while the efficiency of NIBIDC is more than CCBBC. The topology structure of the NIBIDC is simple and easy to control. The performance analysis under steady-state condition of the novel converter is carried out and a detailed comparison with CCBBC is done in connection to switching stress, converter efficiency and duty ratios to output power, etc. The operation details for proposed NIBIDC in both mode is verified/validated by experimenting with 20V input for different duty ratios in charging and discharging state of a battery and the results infer to be identical with theoretical analysis.

For stabilizing the common-mode output voltage of fully differential operational amplifiers, switched-capacitor (SC) type of common-mode feedback (CMFB) is a familiar technique. This is appropriate for implementing high-gain wide-swing low-power op-amps due to its benefits of minimum power consumption, superior linearity across a large amplifier output swing range, and improved feedback loop stability in comparison to continuous-time CMFB. However, the usage of SC-CMFB requires careful attention to some realistic aspects, details of many of which are available in literature. Nonetheless, its adverse effect on the op-amp’s differential-mode gain has not been investigated much. The explanation for this effect is the SC-CMFB-induced equivalent resistive loading, and this is particularly significant in amplifiers like folded cascode which are intended to provide a high gain. This issue of drop in op-amp dc gain because of SC-CMFB, and the consequence on the realization of continuous-time and discrete-time forms of integrators utilizing such amplifiers is the topic of discussion in this paper. Relevant analytical derivations and circuit simulations at the transistor level are provided. A couple of design guidelines and circuit topologies for minimizing the loading-induced gain reduction are also presented.

This paper deals with the experimental realization of square/triangular wave generator using commercially available ICs. A prototype of extra-X second generation current conveyor and five passive components are used in the experimental setup. The proposed generator provides both square and triangular waveforms simultaneously in voltage-mode. The circuit enjoys the feature of independent controllability of oscillation frequency via grounded resistor/grounded capacitor. A range of oscillation frequency from 3Hz to 250Hz is easily achieved via variation in one of the grounded resistors for a fixed value of capacitor. Moreover, a range of oscillation frequency from 19.8Hz to 19.2kHz can be achieved through the variation in grounded capacitor. The experimental results show that the performance of the proposed generator is good at operating frequency as low as at 19.8 Hz and as high as 19.2kHz. Therefore, the proposed circuit can operate well from extra-low-frequency range to very-low-frequency range. Furthermore, the maximum nonlinearity of oscillation frequency is found to be 4% only.

A WSN system incorporates a gateway that provides wireless connectivity back to the wired world and distributed nodes. Many existing schemes were utilized for the purpose of increasing the data gathering capacity of sensor nodes from source to sink node. But the existing schemes suffered from maximum distance problem of reaching the sink node. Hence, to overcome those issues, we propose an energy efficient data gathering technique in WSN. Initially, in this paper, the sensor nodes are clustered using LEACH protocol. After the clustering process, cluster heads (CHs) are selected. These selected CHs in all the clusters are used for transferring the messages to the mobile node for data gathering. Then, optimal data transmission path is selected with the help of Optimal Minimum Covering Spanning Tree (OMST) algorithm. The OMST algorithm enhances data gathering and reduces the duration for reaching the sink node via selection of polling points. For reducing time complexity in MST, an efficient optimization algorithm is used. For an optimization purpose, particle gene swarm (PGS) model is used. From the experimental results, the proposed method achieved better results than the existing method in terms of energy, overhead, delay, delivery ratio, NLT and throughput.

The heterogeneous distributed embedded systems integrated of multiple functions with different criticality levels are multi-functional mixed-criticality systems (MMCSs). The state-of-the-art work has studied the real-time scheduling in MMCS; however, it is not well designed in system switching mechanism and operation which may lead to missing the deadlines of high-criticality functions and redundant operation. In this study, we improve and optimize the problem by developing an algorithm called rearrangement-based scheduling for MMCS (RSM). The RSM algorithm optimizes the following two main aspects. The first aspect is optimizing system-criticality switching mechanisms, including system criticality changed up and down. The second aspect is the effective operation in system-criticality switching to reduce redundant operation. Experiments are performed, and results show that the RSM algorithm can achieve lower overall makespan and deadline miss ratios (DMRs) than the existing algorithms.

Edge is basically the symbol and reflection of partial image discreteness. It is one of the most commonly used operations in image processing and pattern recognition, it contains a wealth of internal information leading to strong interpretation of image. Resisting against noise, illumination and extracting appropriate features from an image is a great challenge in many computer vision applications. Indeed this topic participates to reduce the handled information and focuses on those related to existing objects. Efficient and accurate edge detection will lead to increase in the performance of many computer vision applications, including image segmentation, object-based image coding and image retrieval. Contour detection contributes to locate pixel sets which correspond to sudden intensities variation, these unstable properties of the given image commonly suggest to important events on going in the scene. In this paper, we present in the first time a novel and robust method for edge detection based on joint and conditional entropy when we highlight a Shannon theory, the second part of this paper is dedicated to decision making of edge pixels membership by intelligent method based on fuzzy logic tool.

This paper presents an alphanumeric pattern recognition approach based on memristive crossbar circuit using perceptron learning rule. The proposed approach incorporates a memristive crossbar-based learning and training circuit (TC) module (i.e., synaptic network) and an operational amplifier (op-amp)-based neuron. Alphanumeric patterns, such as alphabets (A–Z) and numerics (0–9), are applied on the TC module and it adjusts the synaptic weights using the perceptron learning rule. The TC module includes 16 inputs, which are interconnected to nine output neurons through memristors. The input and output patterns are represented through $4\times 4$ and $3\times 3$ matrix pixels, respectively. This proposed circuit has implemented all alphanumeric patterns, such as alphabets (A–Z) and numerics (0–9), successfully. However, only the pattern “A” is illustrated in detail for better understanding. SPICE simulation results supported by analytical calculations of pattern “A” are reported. The average power consumption for the proposed approach using memristor is 77.77% lower than the conventional MOSFET-based approach, apart from significant saving of silicon overhead in contrast to its counterpart approach.

In this paper, a three-dimensional Space Vector Modulation (3D SVM) is implemented for minimization of Common-Mode Voltage (CMV) of five-level Neutral Point Clamped (NPC) inverter. The 3D SVM control includes all merits of 2D SVM and provides better control compared to other PWM strategies. The switching state vectors are selected based on the nearest vector Switching State Vector (NSV); it selects the switching vectors which are having the minimum CMV level. It leads to minimization of the bearing voltage and protection of the drive from the damage; also this system reduces the total harmonic distortion. The switching time is calculated by reference vector identification with large and small subcubes tracking and prisms tracking in 3D cubic region. The CMV level with 3D SVM scheme is compared with other PWM methods. The simulation and hardware results are verified using Matlab Simulink and FPGA processor.

Power converters are used in a wide range of industrial processes. Computational complexity, tracking ability, and calculation accuracy are the main parameters that affect the switching performance of power converters. One of the major parts of switch-mode power converters is the controllers which are essential for proper operation. A new adaptive controller is proposed to reduce the computational complexity, the algorithm is presented based on Improved Variable Forgetting Factor (IVFF), Leading Dichotomous Coordinate Descent (DCD), and Exponentially-weighted Recursive Least Square (ERLS). The proposed method estimates the system coefficients with 98% accuracy. The settling time of the output voltage is 0.008ms which is faster than other algorithms. According to Leading DCD, this structure needs no multiplier and divider blocks. VFF leads to the improvement of the tracking ability and convergence rate in the system variations. This structure can be implemented on any application that needs an optimal controller. The Vedic mathematics as a multiplier operation is used in the structure of the improved VFF for reducing the calculation delay and area. The error of the proposed method converges to zero with lower than 60 iterations. In other words, the proposed algorithm calculates the optimal coefficients with lower than 50 iterations and is faster than another algorithm.

Multiple-input multiple-output (MIMO) Minimum mean-square error (MMSE) receivers are widely adopted in the latest communication standards and reducing the complexity of these receivers while preserving the error performance is highly desirable. In this work, we study the error performance and implementation complexity of MIMO MMSE receivers when combined with a coordinate interleaved signal space diversity (SSD) technique. Contrary to the well-known trade-off between the error performance and implementation complexity, the proposed system leads to a considerably simplified MIMO MMSE receiver with significant performance gains when compared to the original MIMO MMSE receiver. Unlike the standard MIMO MMSE receiver, the proposed coordinate interleaved technique induces a block diagonal transmit correlation matrix providing both performance enhancement and complexity reduction. The results show that the error performance can be improved more than 10dB with up to 71% computational complexity reduction. The complexity comparison between the original and proposed approaches is also verified by means of field-programmable gate array (FPGA) implementation.

In this paper, we report a new third-order chaotic jerk system with double-hump (bimodal) nonlinearity. The bimodal nonlinearity is of basic interest in biology, physics, etc. The proposed jerk system is able to exhibit chaotic response with proper choice of parameters. Importantly, the chaotic response is also obtained from the system by tuning the nonlinearity preserving its bimodal form. We analytically obtain the symmetry, dissipativity and stability of the system and find the Hopf bifurcation condition for the emergence of oscillation. Numerical investigations are carried out and different dynamics emerging from the system are identified through the calculation of eigenvalue spectrum, two-parameter and single parameter bifurcation diagrams, Lyapunov exponent spectrum and Kaplan–Yorke dimension. We identify that the form of the nonlinearity may bring the system to chaotic regime. Effect of variation of parameters that controls the form of the nonlinearity is studied. Finally, we design the proposed system in an electronic hardware level experiment and study its behavior in the presence of noise, fluctuations, parameter mismatch, etc. The experimental results are in good analogy with that of the analytical and numerical ones.

As many digital signal processing (DSP) applications such as digital filtering are inherently error-tolerant, approximate computing has attracted significant attention. A multiplier is the fundamental component for DSP applications and takes up the most part of the resource utilization, namely power and area. A multiplier consists of partial product arrays (PPAs) and compressors are often used to reduce partial products (PPs) to generate the final product. Approximate computing has been studied as an innovative paradigm for reducing resource utilization for the DSP systems. In this paper, a 4:2 approximate compressor-based multiplier is studied. Approximate 4:2 compressors are designed with a practical design criterion, and an approximate multiplier that uses both truncation and the proposed compressors for PP reduction is subsequently designed. Different levels of truncation and approximate compression combination are studied for accuracy and electrical performance. A practical selection algorithm is then leveraged to identify the optimal combinations for multiplier designs with better performance in terms of both accuracy and electrical performance measurements. Two real case studies are performed, i.e., image processing and a finite impulse response (FIR) filter. The design proposed in this paper has achieved up to 16.96% and 20.81% savings on power and area with an average signal-to-noise ratio (SNR) larger than 25dB for image processing; similarly, with a decrease of 0.3dB in the output SNR, 12.22% and 30.05% savings on power and area have been achieved for an FIR filter compared to conventional multiplier designs.

A reconfigurable architecture is presented to be compatible with conventional passive operating mode and active mode for ultrahigh frequency (UHF) and radio-frequency identification (RFID) tag. The transceiver with frequency locked on-chip oscillator is proposed to increase the read range of RFID system and the lifetime of tag. The transceiver is fabricated in 0.18$\mu$m standard CMOS process with the active area of 0.246mm². For passive mode, the sensitivity of tag is $-17$dBm. For the active mode, the sensitivity is $-32$dBm only consuming 1.2$\mu$W under the supply voltage of 0.8V. The output power is $-10$dBm for active transmitting mode and the power consumption is 450$\mu$W under the supply voltage of 1V.

This paper explores the design and analysis of 20nm tunnel transistor-based Exclusive-OR (Ex-OR) gates and half-adder cells with circuit interaction (co-design) approach for energy efficient and reliable computing architectures at scaled supply voltages (50–300mV). TFETs have attracted much attention recently for energy efficient system designs. The circuit interaction is made possible for designing more consistent functional architectures at the minimum power supply of 50–300mV. Using this technique, the core computational blocks of basic adder blocks and Ex-OR gates are designed with TFET as a fundamental device and the whole design procedure is elaborated in this paper. The primary classifications of Tunnel FETs, viz. Homo-junction TFET (HoJn TFET) and Hetero-junction TFETs (HeJn TFET) are investigated thoroughly under different constraints specifically at the device configurations. By considering the above-mentioned subtypes of TFETs, three variants of Ex-OR primitive gates are modeled and are named with respect to the use of transistors as static complementary TFET-12T (SC12T), Transmission Gate logic-8T (TG8T) and Improved Transmission Gate logic-6T (ITG6T) Ex-OR gate designs. The benchmarking of the proposed gates is done using double-gate Si FinFET at 20nm technology. Amongst all the three proposed Ex-OR designs of SC12T, TG8T and ITG6T in addition to that of LVT and HVT FinFET/CMOS, only ITG6T is the designer’s choice by offering the minimum power consumption as well as high energy, improved choice compared to the other two styles of designs and also when robustness and reliability are taken into account, SC12T and TG8T designs are not providing the full swing of outputs. The minute glitch with that of ITG6T designs is a lesser reliability feature and for this the best alternative is TFET TG8T by providing suppressed over shoots and enhanced transition speed. From the performed multi simulations under different critical conditions and at supply voltage of 100mV, it is being demonstrated that the energy efficient circuit option is the SC12T and ITG6T Ex-OR designs which are validated with the steep slope characteristics of TFET’s and also these two designs offer reliability advantage. The major restrictions from the energy efficiency issues are eliminated and disclosed in the HoJn TFETs and HeJn TFET by using circuit co-design methodology and TFETs steep slope characteristics.